Re: inversion MOSFET against enhancement MOSFET
jfyan said:
yes, the serial connection of two caps will reduce the overall capacitance for small |Vpoly|, but with more negative Vpoly, the overall cap is still close to cox, because any small disturbance on Vpoly results in the change of "hole" only. this is because the amount of "hole" is much larger than the fixed charge. this means, the cap from junction is shorted.
Hi Jeff,
what do you mean with "hole"? Is it identical with the p+ inversion layer, which is built up when the negative Vpoly voltage surmounts the strong-inversion surface potential + Vt ?
In this case you're right saying "any small disturbance on Vpoly results in the change of "hole"", the change being an increase of carrier concentration just below the gate oxide in the n-well at the interface between oxide and silicon, with negligible thickness change.
This p+ inversion layer, however, constitutes a reversely polarized junction to the n-well in series with the gate cap, generating a depletion layer in this n-well, which is considerably thicker than the gate oxide (but has an εr about 3 times larger than that of the gate oxide).
Let's try an example: For a 0.18µm CMOS process, the gate oxide thickness is ≈4nm,
whereas the depletion layer thickness for (Vpoly-Vwell)=-2V creates a depletion layer thickness of about 40nm (The strong-inversion surface potential PHI(s) "eats up" about -1V , hence a residual reverse voltage of -1V is left over for the depletion region, s. the cited text from David M. Binkley's book below). This results in a cap/area ratio which is about a factor of 3 lower than that of the gate oxide cap. Being in series with the this cap, it essentially
determines the total cap/area ratio.
I do not understand what you mean with "the cap from junction is shorted". What should short-cut this junction? The p+ inversion layer (your "hole"?) isn't directly connected to the n-well, only via the cap of the reversely polarized junction cap.
If you have a different opinion, just tell me, or simulate such a cap!
Regards, erikl
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Citation from David M. Binkley:
"Tradeoffs and Optimization in Analog CMOS Design" p. 235
"For a 0.18µm CMOS process having [a retrograde n-well doping of] NB = 7e-17/cm³, the depletion region thickness is tdep = 0.043µm. This assumes VSB = 0V , PHI(0) = 2*PHI(F) = 0.913V at T=300K, and an approximate strong-inversion surface potential of PHI(s) = PHI(0) ≈ 2*PHI(F) + 4UT ≈ 1 V."
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