Pipeline ADC Sub-DAC Linearity Problem ?

[thehighpolu]

Hello,

I'm designing an 8-bit pipeline ADC using 1.5-bit MDAC stages. I am using a flip-around architecture and having trouble with the transistor-level implementation of the switches. I have differential dynamic latch comparator with decoder circuit and they controll the parallel tg switches of dac that connects to vcm vrefp vrefn. My ADC's analog portion works fine with ideal switches while everything else is at the transistor level. However, when I switch to transmission gate switches for sample-and-hold and especially for DAC switches, I observe nonlinearities, as shown in the figure below.

Figure 1: ramp test of the first two stages, sampled mdac outputs

*I'm sampling at the end of the hold period, where comparators are deciding...

Figure 2: Close up to when two DACs are switching at the same time.

figure 3: Additionally timedomain output of two stages, red: 1st stage, yellow 2nd stage.

Have you had any similar issues before, or can you point me in the right direction? I've been tweaking this issue for the past few weeks...

Thank you all for your time!

 

[dick_freebird]

How about staggering clocks? Some of it looks pretty busy.

Hard switched tgate will have common mode dependence and source impedance dependence at best, of the direction and magnitude of the kick. How's gate drive skew look? Any kickback from other side?

Try less drive on the tgate gates, resistor or long channel to soften the bumps.

 

[sidun.av]

I can recommend eating a cake with small bites - replace only one switch first and track control/input/output signal performance. You can also try to make a simple testbench with a test signal and your switch and check if you have the same problem. It should help understanding the root cause of the problem.
It's hard to guess the problem without seeing the schematic and corresponding waveforms.

One of the possible reasons might be the charge injection problem:

What is Charge Injection and Cancellation Techniques in Analog CMOS Switches (T-Gates) - Mis Circuitos

How to avoid charge injection in CMOS analog switches, its effect on voltage glitches, and techniques for cancellation, including complementary switches, dummy transistors…

miscircuitos.com