hank_deng said:HI, All:
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the mom-cap array.
The adjacent mom_cap value ratio shoule be 2. But in post-simulation the wost ratio is 1.985 and 2.02. The mom_cap value is extracted from layout by Assura, the floorplan of the mom_cap array is concentrical of all bit. The inter-connection
of layout is good, no obvious extra parasitic cap. If the floorplan fo the mom_cap array is bit by bit, the ratio the mom_cap value is a little bettle, and the ENOB is 9bit.
I wonder the post-simulation results is believable? the mom_cap value is presice from Assura?
Thanks for answer and welcome for discussion!
timof said:hank_deng said:HI, All:
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the mom-cap array.
The adjacent mom_cap value ratio shoule be 2. But in post-simulation the wost ratio is 1.985 and 2.02. The mom_cap value is extracted from layout by Assura, the floorplan of the mom_cap array is concentrical of all bit. The inter-connection
of layout is good, no obvious extra parasitic cap. If the floorplan fo the mom_cap array is bit by bit, the ratio the mom_cap value is a little bettle, and the ENOB is 9bit.
I wonder the post-simulation results is believable? the mom_cap value is presice from Assura?
Thanks for answer and welcome for discussion!
Do you "block" the MOM-capacitors from parasitic extraction (and use their SPICE models in the nelist instances), or do you extract all MOM capacitors with Assura?
Can you check if MIM capacitor metal layers are present in the technology file (procfile/p2lvsfile)?
I attach a short application note that discusses the issues of accuracy in capacitance extraction in application to MOM caps and ADCs.
Max
-----------
The report mentions "a rigorous field solver extraction (~0.1%)" which corresponds to a resolution of ≈10 bit. Isn't that too low for an accurate parasitics extraction for a 12bit-ADC ?hbchens said:Hi, timof
you mean you can provide accurate parasitic capacitance extration for SAR ADC's design?timof said:"Accurate extraction of parasitic capacitance helps ensure linearity of SAR ADCs"
Maxim Ershov
Silicon Frontline Technology, Millich Dr., Suite 206, Campbell, CA 95008, USA
Phone: 1-408-963-6916, Fax: 1-408-963-6906, E-mail: maxim(at)siliconfrontline.com
erikl said:The report mentions "a rigorous field solver extraction (~0.1%)" which corresponds to a resolution of ≈10 bit. Isn't that too low for an accurate parasitics extraction for a 12bit-ADC ?hbchens said:Hi, timof
you mean you can provide accurate parasitic capacitance extration for SAR ADC's design?timof said:"Accurate extraction of parasitic capacitance helps ensure linearity of SAR ADCs"
Maxim Ershov
Silicon Frontline Technology, Millich Dr., Suite 206, Campbell, CA 95008, USA
Phone: 1-408-963-6916, Fax: 1-408-963-6906, E-mail: maxim(at)siliconfrontline.com
I guess standard extraction tools (assura, calibre) can assure ;-) a much better relative extraction accuracy -- otherwise I wouldn't have been able to design and layout a (planned) 12bit ADC. The final ENOB of 11bit already had been shown by the postLayout simulation.timof said:... The question of original poster was concerned with standard parasitic extractors' accuracy - which can not guarantee ~1% of extraction accuracy.
You're right, I've overlooked this. However, for the resistor divider's 6 LSBs, you'd still need a ≈250 ppm extraction (in)accuracy, which would require a computing time factor of 16 more than for a 0.1% inaccuracy. Is it possible to restrict the required extraction resolution to predefined areas?timof said:Also, MOM capacitance array in their 12 bit ADC was used only for 6 MSB - and I am not sure if you need accuracy better than 0.1% to resolve 6 bits (this is to address erikl's question).
Max
----------
erikl said:I guess standard extraction tools (assura, calibre) can assure ;-) a much better relative extraction accuracy -- otherwise I wouldn't have been able to design and layout a (planned) 12bit ADC. The final ENOB of 11bit already had been shown by the postLayout simulation.
----------
erikl said:Is it possible to restrict the required extraction resolution to predefined areas?
Rgds, erikl
Ok, I didn't try that. May be I was just lucky with the rather good matching between postLayout simulation results and silicon reality. I think the achievable accuracy depends very much on the quality of the parasitics' modeling and of the extraction rules. For a mature process (0.35µm), I guess the available extraction accuracy also has been developped quite well.timof said:Try a couple of things:
1. create a layout with a large number of identical structures (like an array), and look at the distribution of the extracted capacitance values.
2. create a layout and rotate it by 90 degree - and check if your extracted capacitance value remains the same.
A list of issues can be continued...
Good to hear that, Max, thank you!timof said:F3D allows to specify (prior to simulation/extraction, in the input deck!) different extraction accuracy for different nets - for example, high accuracy for critical nets, and relaxed accuracy for other nets, to find the optimum trade-off between accuracy and performance.
For a mature process (0.35µm), I guess the available extraction accuracy also has been developped quite well.
Not at all. Try a couple of things:
1. create a layout with a large number of identical structures (like an array), and look at the distribution of the extracted capacitance values.
2. create a layout and rotate it by 90 degree - and check if your extracted capacitance value remains the same.
A list of issues can be continued...
Thank you, but just 11bit ENOB - in postLayout sim. and silicon reality. But that's quite normal, I guess.hbchens said:But still congratulate you achieve 12-bit resolution.
No paper, sorry! This was timely high pressure free lancing work with a team. Quite a lot of papers already have been published on such ADCs. We used the general structure of a cyclic-redundancy 10bit ADC (s. below) and pushed it to 12bit (i.e. 11bit ENOB) with very thorough layout of the caps' arrays, keeping the (Calibre) extracted parasitics' differences < 0.025%.hbchens said:By the way,what time we can share your experience from publication?
hbchens said:erikl wrote:
Hi,Max
I have three questions:
first:What's the advantage of F3D tool compared with the QuickCap ?As I know,the QuickCap also use random walk method to extract the parasitic of interconnect capacitance.
second:As I know,all the interconnect capacitance extraction tools are for purpose of VLSI parasitical extraction (5% accuracy is enough for many digital circuits,but that's not enough for many analog circuits).So how to guarantee these tools suit for accuracy requirement of analog design,such as the case of 12-bit SAR ADC capacitors array?
third: How many silicon proved measurement results can prove F3D tool has better than 0.1% accuarcy?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?