Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

The presicion of mom-cap in 12bit ADC

Status
Not open for further replies.

hank_deng

Newbie level 5
Joined
Jul 19, 2009
Messages
8
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Location
suzhou
Activity points
1,353
HI, All:
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the mom-cap array.
The adjacent mom_cap value ratio shoule be 2. But in post-simulation the wost ratio is 1.985 and 2.02. The mom_cap value is extracted from layout by Assura, the floorplan of the mom_cap array is concentrical of all bit. The inter-connection
of layout is good, no obvious extra parasitic cap. If the floorplan fo the mom_cap array is bit by bit, the ratio the mom_cap value is a little bettle, and the ENOB is 9bit.
I wonder the post-simulation results is believable? the mom_cap value is presice from Assura?
Thanks for answer and welcome for discussion!
 

shanmei

Advanced Member level 1
Joined
Jul 26, 2006
Messages
428
Helped
8
Reputation
16
Reaction score
8
Trophy points
1,298
Location
USA
Activity points
4,480
can you use a bigger cap unit?

where is the error from? from the parasitic line or something else?
get those line far way from the critical cap.
 

timof

Advanced Member level 2
Joined
Feb 21, 2008
Messages
641
Helped
213
Reputation
426
Reaction score
206
Trophy points
1,323
Location
San Jose, CA, USA
Activity points
6,808
hank_deng said:
HI, All:
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the mom-cap array.
The adjacent mom_cap value ratio shoule be 2. But in post-simulation the wost ratio is 1.985 and 2.02. The mom_cap value is extracted from layout by Assura, the floorplan of the mom_cap array is concentrical of all bit. The inter-connection
of layout is good, no obvious extra parasitic cap. If the floorplan fo the mom_cap array is bit by bit, the ratio the mom_cap value is a little bettle, and the ENOB is 9bit.
I wonder the post-simulation results is believable? the mom_cap value is presice from Assura?
Thanks for answer and welcome for discussion!

Do you "block" the MOM-capacitors from parasitic extraction (and use their SPICE models in the nelist instances), or do you extract all MOM capacitors with Assura?

Can you check if MIM capacitor metal layers are present in the technology file (procfile/p2lvsfile)?

I attach a short application note that discusses the issues of accuracy in capacitance extraction in application to MOM caps and ADCs.

Max
-----------
 

hbchens

Junior Member level 3
Joined
Aug 29, 2004
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
282
timof said:
hank_deng said:
HI, All:
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the mom-cap array.
The adjacent mom_cap value ratio shoule be 2. But in post-simulation the wost ratio is 1.985 and 2.02. The mom_cap value is extracted from layout by Assura, the floorplan of the mom_cap array is concentrical of all bit. The inter-connection
of layout is good, no obvious extra parasitic cap. If the floorplan fo the mom_cap array is bit by bit, the ratio the mom_cap value is a little bettle, and the ENOB is 9bit.
I wonder the post-simulation results is believable? the mom_cap value is presice from Assura?
Thanks for answer and welcome for discussion!

Do you "block" the MOM-capacitors from parasitic extraction (and use their SPICE models in the nelist instances), or do you extract all MOM capacitors with Assura?

Can you check if MIM capacitor metal layers are present in the technology file (procfile/p2lvsfile)?

I attach a short application note that discusses the issues of accuracy in capacitance extraction in application to MOM caps and ADCs.

Max
-----------


Hi,timof

"Accurate extraction of parasitic capacitance
helps ensure linearity of SAR ADCs
Maxim Ershov
Silicon Frontline Technology, Millich Dr., Suite 206, Campbell, CA 95008, USA
Phone: 1-408-963-6916, Fax: 1-408-963-6906, E-mail: maxim@siliconfrontline.com"

you means you can provide accurate parasitic capacitance extration for SAR ADC's design?
 

erikl

Super Moderator
Staff member
Joined
Sep 9, 2008
Messages
8,112
Helped
2,689
Reputation
5,358
Reaction score
2,291
Trophy points
1,393
Location
Germany
Activity points
44,155
hbchens said:
Hi, timof
timof said:
"Accurate extraction of parasitic capacitance helps ensure linearity of SAR ADCs"
Maxim Ershov
Silicon Frontline Technology, Millich Dr., Suite 206, Campbell, CA 95008, USA
Phone: 1-408-963-6916, Fax: 1-408-963-6906, E-mail: maxim(at)siliconfrontline.com
you mean you can provide accurate parasitic capacitance extration for SAR ADC's design?
The report mentions "a rigorous field solver extraction (~0.1%)" which corresponds to a resolution of ≈10 bit. Isn't that too low for an accurate parasitics extraction for a 12bit-ADC ?
 

hbchens

Junior Member level 3
Joined
Aug 29, 2004
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
282
erikl said:
hbchens said:
Hi, timof
timof said:
"Accurate extraction of parasitic capacitance helps ensure linearity of SAR ADCs"
Maxim Ershov
Silicon Frontline Technology, Millich Dr., Suite 206, Campbell, CA 95008, USA
Phone: 1-408-963-6916, Fax: 1-408-963-6906, E-mail: maxim(at)siliconfrontline.com
you mean you can provide accurate parasitic capacitance extration for SAR ADC's design?
The report mentions "a rigorous field solver extraction (~0.1%)" which corresponds to a resolution of ≈10 bit. Isn't that too low for an accurate parasitics extraction for a 12bit-ADC ?


Hi, timof
(~0.1%) is the relative precision(for example:C2/C1) or absolute precision for a MOM capacitor?
Does this tool(F3D) use table-based method to caculate parasitic capacitors?


Hi,erikl
Thanks for your reminding.For a 12-bit SAR, the tool is not enough accuracy.
I think it's only can help the designer to check the big parasitic capacitance for matching request.
But as I know,the 12-bit resolution,for passive device(R,C......) matching,is limited by general process variation,not only by tool accuracy.

By the way,what I have mentioned is from the product(yield......) challenge,not paper work demand.
 

timof

Advanced Member level 2
Joined
Feb 21, 2008
Messages
641
Helped
213
Reputation
426
Reaction score
206
Trophy points
1,323
Location
San Jose, CA, USA
Activity points
6,808
hbchens -

The value of ~0.1% quoted in the application note is a conservative estimate of the absolute tool accuracy. Testing it for accuracy better than 0.1% is very tricky. It's hard to find reliable reference data. On several simple test cases that permit analytical solution for capacitance, F3D has been proven to provide better than 0.01% absolute accuracy. On more complicated (realistic) layouts, wherever it was possible to obtain a reliable reference data, limited by 0.1% accuracy, F3D was within ~0.1% from the reference values.

That being said, it's probably meaningless to look at absolute capacitance value with very high accuracy - as in real designs capacitance will be varying by more than 5% 9probably 10-15%) due to inevitable process variations. However - the ratio of capacitance values of closely spaced capacitors (matching) should be insensitive to process variations. Matching may be violated due to "un-matched" parasitics. So, for extreme accuracy (0.1% or better), it is the ratio of capacitance values that is of primary concern.

On several occasions, our customers had to run F3D with accuracy of 0.01% (remember that getting 0.01% accuracy takes 100x times longer than 0.1% accuracy using random walk method) - to get a very good agreement between measurements data (INL and DNL) and simulations utilizing F3D parasitic extraction results.

The question of original poster was concerned with standard parasitic extractors' accuracy - which can not guarantee ~1% of extraction accuracy. Also, MOM capacitance array in their 12 bit ADC was used only for 6 MSB - and I am not sure if you need accuracy better than 0.1% to resolve 6 bits (this is to address erikl's question).

If you have a real problem with ADC linearity caused by capacitance ratio mismatch (layout, parasitics, etc.) - let's discuss this offline.

Max
----------
 

erikl

Super Moderator
Staff member
Joined
Sep 9, 2008
Messages
8,112
Helped
2,689
Reputation
5,358
Reaction score
2,291
Trophy points
1,393
Location
Germany
Activity points
44,155
timof said:
... The question of original poster was concerned with standard parasitic extractors' accuracy - which can not guarantee ~1% of extraction accuracy.
I guess standard extraction tools (assura, calibre) can assure ;-) a much better relative extraction accuracy -- otherwise I wouldn't have been able to design and layout a (planned) 12bit ADC. The final ENOB of 11bit already had been shown by the postLayout simulation.

timof said:
Also, MOM capacitance array in their 12 bit ADC was used only for 6 MSB - and I am not sure if you need accuracy better than 0.1% to resolve 6 bits (this is to address erikl's question).
Max
----------
You're right, I've overlooked this. However, for the resistor divider's 6 LSBs, you'd still need a ≈250 ppm extraction (in)accuracy, which would require a computing time factor of 16 more than for a 0.1% inaccuracy. Is it possible to restrict the required extraction resolution to predefined areas?
Rgds, erikl
 

timof

Advanced Member level 2
Joined
Feb 21, 2008
Messages
641
Helped
213
Reputation
426
Reaction score
206
Trophy points
1,323
Location
San Jose, CA, USA
Activity points
6,808
erikl said:
I guess standard extraction tools (assura, calibre) can assure ;-) a much better relative extraction accuracy -- otherwise I wouldn't have been able to design and layout a (planned) 12bit ADC. The final ENOB of 11bit already had been shown by the postLayout simulation.
----------

Not at all. Try a couple of things:

1. create a layout with a large number of identical structures (like an array), and look at the distribution of the extracted capacitance values.

2. create a layout and rotate it by 90 degree - and check if your extracted capacitance value remains the same.

A list of issues can be continued...

erikl said:
Is it possible to restrict the required extraction resolution to predefined areas?
Rgds, erikl

F3D allows to specify (prior to simulation/extraction, in the input deck!) different extraction accuracy for different nets - for example, high accuracy for critical nets, and relaxed accuracy for other nets, to find the optimum trade-off between accuracy and performance.
 

erikl

Super Moderator
Staff member
Joined
Sep 9, 2008
Messages
8,112
Helped
2,689
Reputation
5,358
Reaction score
2,291
Trophy points
1,393
Location
Germany
Activity points
44,155
timof said:
Try a couple of things:

1. create a layout with a large number of identical structures (like an array), and look at the distribution of the extracted capacitance values.

2. create a layout and rotate it by 90 degree - and check if your extracted capacitance value remains the same.

A list of issues can be continued...
Ok, I didn't try that. May be I was just lucky with the rather good matching between postLayout simulation results and silicon reality. I think the achievable accuracy depends very much on the quality of the parasitics' modeling and of the extraction rules. For a mature process (0.35µm), I guess the available extraction accuracy also has been developped quite well.

timof said:
F3D allows to specify (prior to simulation/extraction, in the input deck!) different extraction accuracy for different nets - for example, high accuracy for critical nets, and relaxed accuracy for other nets, to find the optimum trade-off between accuracy and performance.
Good to hear that, Max, thank you!
Rgds, erikl
 

hbchens

Junior Member level 3
Joined
Aug 29, 2004
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
282
erikl wrote:
For a mature process (0.35µm), I guess the available extraction accuracy also has been developped quite well.

Yes,you are right. Because the MOM cap model is quite well.But still congratulate you achieve 12-bit resolution.By the way,what time we can share your experience from publication?

timof wrote:
Not at all. Try a couple of things:

1. create a layout with a large number of identical structures (like an array), and look at the distribution of the extracted capacitance values.

2. create a layout and rotate it by 90 degree - and check if your extracted capacitance value remains the same.

A list of issues can be continued...

what timof have mentioned above are real problems when used the interconnection metals(for example:use M1,M2,M3,M4,M5) as capacitor below .18um process .
By the way,this kinds of capacitor can be designed as any shape for considering to
reduce die size or decrease harmful parasitical capacitance.

Hi,Max
I have three questions:
first:What's the advantage of F3D tool compared with the QuickCap ?As I know,the QuickCap also use random walk method to extract the parasitic of interconnect capacitance.
second:As I know,all the interconnect capacitance extraction tools are for purpose of VLSI parasitical extraction (5% accuracy is enough for many digital circuits,but that's not enough for many analog circuits).So how to guarantee these tools suit for accuracy requirement of analog design,such as the case of 12-bit SAR ADC capacitors array?
third: How many silicon proved measurement results can prove F3D tool has better than 0.1% accuarcy?
 

erikl

Super Moderator
Staff member
Joined
Sep 9, 2008
Messages
8,112
Helped
2,689
Reputation
5,358
Reaction score
2,291
Trophy points
1,393
Location
Germany
Activity points
44,155
hbchens said:
But still congratulate you achieve 12-bit resolution.
Thank you, but just 11bit ENOB - in postLayout sim. and silicon reality. But that's quite normal, I guess.

hbchens said:
By the way,what time we can share your experience from publication?
No paper, sorry! This was timely high pressure free lancing work with a team. Quite a lot of papers already have been published on such ADCs. We used the general structure of a cyclic-redundancy 10bit ADC (s. below) and pushed it to 12bit (i.e. 11bit ENOB) with very thorough layout of the caps' arrays, keeping the (Calibre) extracted parasitics' differences < 0.025%.
 

timof

Advanced Member level 2
Joined
Feb 21, 2008
Messages
641
Helped
213
Reputation
426
Reaction score
206
Trophy points
1,323
Location
San Jose, CA, USA
Activity points
6,808
hbchens said:
erikl wrote:

Hi,Max
I have three questions:
first:What's the advantage of F3D tool compared with the QuickCap ?As I know,the QuickCap also use random walk method to extract the parasitic of interconnect capacitance.
second:As I know,all the interconnect capacitance extraction tools are for purpose of VLSI parasitical extraction (5% accuracy is enough for many digital circuits,but that's not enough for many analog circuits).So how to guarantee these tools suit for accuracy requirement of analog design,such as the case of 12-bit SAR ADC capacitors array?
third: How many silicon proved measurement results can prove F3D tool has better than 0.1% accuarcy?

Hi hbchens - sorry for a late reply:

1. F3D extracts not only capacitance, but also distributed RC netlists; does not require a special "database" - instead it reads directly either GDS file, or any of the existing LVS databases (Calibre, Hercules, Assura) and applies all manufacturing effects as described in technology (itf, proc, ict, ircx) files; offers powerful capabilities to do "device" or "cell" blocking; there are many more differences, too many to fit into one paragraph.

2. Even on basic patterns (5 straight metal fingers with varying width and spacing, with or without top and/or bottom groundplane) the parasitic extraction tools are off by more than 10% on a significant number of test patterns. For complicated layouts, small coupling capacitances are missed outright. These capacitances are absolutely critical in precision analog circuits requiring capacitance perfect matching or weighting. There is just no way to guarantee that the pattern matching tools would give you a required accuracy - you need to use field solver to guarantee that.

3. Lots of data - please contact me if you would like to have a serious discussion.

Max
----------
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top