hank_deng
Newbie level 5
HI, All:
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the mom-cap array.
The adjacent mom_cap value ratio shoule be 2. But in post-simulation the wost ratio is 1.985 and 2.02. The mom_cap value is extracted from layout by Assura, the floorplan of the mom_cap array is concentrical of all bit. The inter-connection
of layout is good, no obvious extra parasitic cap. If the floorplan fo the mom_cap array is bit by bit, the ratio the mom_cap value is a little bettle, and the ENOB is 9bit.
I wonder the post-simulation results is believable? the mom_cap value is presice from Assura?
Thanks for answer and welcome for discussion!
The project is a 12bit SAR-ADC, the 6 MSBs is binary-weighted mom-cap, the unit is 68fF, and the Msb is 68*32=2176fF. The 6 LSBs is resistor divider.
In the pre-simulation the ENOB is 11bit. But in the post-simulation the ENOB is just 8.6bit. I check the whole project, and find the problem is from the mom-cap array.
The adjacent mom_cap value ratio shoule be 2. But in post-simulation the wost ratio is 1.985 and 2.02. The mom_cap value is extracted from layout by Assura, the floorplan of the mom_cap array is concentrical of all bit. The inter-connection
of layout is good, no obvious extra parasitic cap. If the floorplan fo the mom_cap array is bit by bit, the ratio the mom_cap value is a little bettle, and the ENOB is 9bit.
I wonder the post-simulation results is believable? the mom_cap value is presice from Assura?
Thanks for answer and welcome for discussion!