the p+ resistor in analog design

John Xu said:

Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice simulation?


Thanks in advance

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omsi said:

John Xu said:

Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice simulation?


Thanks in advance

Click to expand...

hi,
yes the parasitic junction capacitance is considered in prelayout simulation.

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John Xu said:

Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice simulation?


Thanks in advance

Click to expand...

alenhan said:

if you have P+ resistor model, it should be included in spice model

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