There are no additional restrictions from Verilog to SystemVerilog in the way you are allowed to connect ports. You just have more options in SystemVerilog. From a language perspective, SystemVerilog does not enforce the direction of data in a port directly; it only restricts the way you are allowed access the port. (i.e. whay types of connections and assignments are allowed.
You are not allowed to use a variable to connect to an inout port no matter where else the variable is used. Only wires (nets) can connect to inout ports. Note that data type logic can be used to declared with a wire as well as a variable.
BTW, SystemVerilog is one word.