The inout port and the system verilog and verilog

[sun_ray]

Suppose inout is declared in the verilog module of a design. Does it mean that there is an enable in the design such that when the enable is high then inout will be input and when the enable is zero the enable is an output.


Suppose a port is an input to a module written in system Verilog and it needs to be connected to an inout port of another module written in system verilog. Can a variable be declared as logic to connect the inout port to the input port of another module? If the variable declared as logic is not the legal way to connect , please response what is the legal way to connect the input port to the inout port in system verilog.

 

[dave_59]

There are no additional restrictions from Verilog to SystemVerilog in the way you are allowed to connect ports. You just have more options in SystemVerilog. From a language perspective, SystemVerilog does not enforce the direction of data in a port directly; it only restricts the way you are allowed access the port. (i.e. whay types of connections and assignments are allowed.

You are not allowed to use a variable to connect to an inout port no matter where else the variable is used. Only wires (nets) can connect to inout ports. Note that data type logic can be used to declared with a wire as well as a variable.

BTW, SystemVerilog is one word.

 

[sun_ray]

Is it that an inout port of a block will have to be connected with an inout port of another block? Is it that the inout port of a block cannot be connected with ports like input or output of another block?



I also asked in the first post that how an inout port of a RTL will be implemented finally at gate level? Will there be an enable pin that will make the inout port as input or output depending on its (Enable pin) value?