Re: test benches
The book recommended by gliss is definetely a must, even though is very oriented to Hardware Verification Languages.
VHDL and Verilog are Hardware Description Languages, so the aim of these languages is to write synthesizable code (even though they have some structures that are not synthesizable).
You can write basic testbenches with vhdl, that will be enough for small designs. The purpose of testbenches is to simulate situations that your design will face when it is synthesized, i.e. bus signals, timing constraints, etc.