The importance of test benches in VHDL coding and rules for writing it

[balakrishna]

Now i am learning vhdl code writing.
Please tell me the importance of test benches in vhdl coding and the rules that have to follow to write test benches?

 

[gliss]

test benches

Try this book: Writing Testbenches, Functional Verification of HDL Models.

 

[mendozaulises]

Re: test benches

The book recommended by gliss is definetely a must, even though is very oriented to Hardware Verification Languages.
VHDL and Verilog are Hardware Description Languages, so the aim of these languages is to write synthesizable code (even though they have some structures that are not synthesizable).
You can write basic testbenches with vhdl, that will be enough for small designs. The purpose of testbenches is to simulate situations that your design will face when it is synthesized, i.e. bus signals, timing constraints, etc.

 

[mmoctar]

Re: test benches

test benches alow you to put define the input of your design and when you run your simulation it will give results according to your input. Like when you want to simulate a counter you can define the cycle of your clock with a test bench file and run it. hope you understand

 

[shraddha]

test benches

hi....
test benches are just models those are used to varify correctness of a HDL model so that u can compare o/p response with expected values.According to that timing information u can see wavforms in ur simulation.it is done before ur simulation.for more details read VLSI design by Dauglas Perry

regards,
shraddha