The impact of the shrinking process window and its effects on parametric yield.

[ameed]

hi all,

With the Moore’s law defining the emerging sub nano technology nodes like 45nm and
32nm, it is high time that the designers who were till now typically concerned about
performance parameters like speed and power also take into consideration the impact of
the shrinking process window and its effects on parametric yield.
Effect of Shrinking Geometries

what effect can be getting releted to speed and power:?:

 

[Hunter_BJUT]

layout design

see the Pic

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https://obrazki.elektroda.pl/70_1187869578.gif

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[khotkar]

layout design

ameed,

I think if technology is shrinking then voltage level also going down. on chip area will take less there DRC rules are changing. Power will increase. I don't know @ speed. you should take care @ electro migration. Channel length will decrease then speed will increase. Velocity saturation effect will come there.
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[lijianheng]

Re: layout design

supply voltage will decrease, speed will be faster, power consumption maybe larger or smaller.

 

[venky442]

Re: layout design

hi FRNDZ,
as the device scalling is shrinked down,power consumtion will get increase due to leakage power dissipations,speed also increases as the device size(length decreases),
electromigration propbems will take into effect,shortchannel effect(velocity saturation) effect also there.

 

[sudhasub]

Re: layout design

as device scales down SiO2 layer thickness decreases which results in leakage of current, to rectify this Hi-K material is used. Speed increases as frequency increases when technology scales down.