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the hierarchical vs. flat layout which is better ? And someone said when gatecounter lower than 350k, use flat layout , above 350k use hierarchical . How do you think the gatecounter of flat and hierarchical.
I think always go for flat if there is a choice. Hierarchical layout always degrade the quality of the result.
Some reasons to use hierarchical layout:
1. The chip is simply to big. This has to be more than 1-2 million placeable instances with the new generation of P&R tools.
2. Some siignificant portion of the design of the chip does not change (e.g. DSP, MPEG Decorder IP) and it may be good to "harden" it into a block to save run-time when the final netlist is ready.
3. Faster turnaround time if you have many engineers/workstation/licenses, and the layout flow is established.
If you want cost down , you may need use flat layout , it can reduce area, and flat layout wire lenght small than hierarchical, flat layout clock tree skew time is small , but flat layout time is very hard, I have read a paper from SNUG. A 1M or 5M ( i have forget) gate counter flat layout need 5 day use ASTRO.