Re: clock gating?
sachinmaheshwari said:
i means in simple language can u explain me?
let me try:
Think about Shut-Down or Standby.
The concept of using that modes is to reduce the power consumption of a system.
Each design contains several block.
It may that all the blocks are activated at a time. but later some of them are not activated because they have no task to do; so there is no need to keep them in active mode because it will consume power for free.
One technique that used to implement "Stand-by" mode is to de-assert the clock that feeds the blocks which the system defines later during its operation that this blocks maybe in inactive mode.
The concept is: While the clock is SWINGing then it will consume power.
The way that we can de-assert clock is by feeding that blocks with PERMANENT level instead of the clock. It is called Gated-Clock.
The name behind Gated-Clock is: Try thinking about AND'gate with two inputs while one input is connected to CLOCK and the other input is connected to ENABLE signal. The output of the AND'gate will feed each block in the design.
So when Enable goes high then the block will be feeded by the system clock else to feeded by permanent level which is LOW.
Actually, Gated-Clock is not implemented as I described upon because it will produces partial clock periods and unwanted glitches at the output of the AND'gate.
There many techniques used to generate Gated-Clock.