The differences between HDL and HVL

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kishore111281

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Can any one explain the differences between HDL and HVL
thanks in advance,
 

HDL vs HVL

HDL --> Hardware description language --> Used to design digital logic Eg: VHDL, Verilog

HVL --> Hardware Verification language --> Used to Functionally verify the digital logic designed using a HDL Eg: e, vera, system-C, system-Verilog
 

Re: HDL vs HVL

Hi,
HDL is used for RTL design.
HVL is used for RTL Verification(Random Verification).

Thanks & Regards,
sri
 

HDL vs HVL

we can use hdl like verilog for the verification also....but the problem is we dont have options like structures in it...thts we prefer hvl for the verification..because it gives more freedom
 

Re: HDL vs HVL

badola said:
we can use hdl like verilog for the verification also....but the problem is we dont have options like structures in it...thts we prefer hvl for the verification..because it gives more freedom
Click to expand...

Now, for this task we use sytem Verilog.
 

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