Re: simulation and synthesis
Simulation is to verify your design. Thus it is first step after your design and coding is done. It is totally software activity where you verify your design using simulators like ModelSim. This step is also called as functional simulation.
Once you have verified your design, you need to target your design into hardware. So you need to convert your RTL into gate level design. Synthesis is divided into three steps: Translation, Optimization and Technology Mapping.
Translation: RTL to gate-level netlists.
Optimization: technology-independent logic-level optimization to reduce hardware for required functionality.
Technology Mapping: technology-independent netlists are transformed into technology-dependent ones.
Synthesis tools do all these steps. Designer needs to specify the optimization constraints, which the synthesis tool tries to meet.
After synthesis there is one more simulation called Timing simulation.
It may appear difficult for the first time but you will understand it as you study more about it. You may not be familiar with some of the terms, feel free to ask any doubts.
Regards,
Jitendra.