The difference between '|' operator and keyword 'or'
Hi,
I have noticed that in Verilog literature, the symbol '|' is often used for OR operations. But at some other places the keyword 'or' is also used.
In most of the always blocks, the keyword 'or' is used, and in if statements, either '|' is used or '||' is used.
So functionally, what is the difference between the two, and where to use what.
Hi,
I have noticed that in Verilog literature, the symbol '|' is often used for OR operations. But at some other places the keyword 'or' is also used.
In most of the always blocks, the keyword 'or' is used, and in if statements, either '|' is used or '||' is used.
So functionally, what is the difference between the two, and where to use what.
The only place the or keyword is allowed is inside an event expression to say wait for this event or that event.
Code Verilog - [expand]
1
2
always@(a or b) ...
always@(posedge clk ornegedge reset) ...
This is in contrast with the boolean logical or || or bit-wise | or operators
Code Verilog - [expand]
1
always@(a || b) ...
which say to wait for the result of the expression to change, not for each operand to change. If a and b were 1, and b changed to 0, the result is still 1 and it would keep waiting.
The logical OR of any number of events can be expressed so that the occurrence of any one of the events
triggers the execution of the procedural statement that follows it. The keyword or or a comma character (,)
is used as an event logical OR operator. A combination of these can be used in the same event expression.
Comma-separated sensitivity lists shall be synonymous to or-separated sensitivity lists.
The next two examples show the logical or of two and three events, respectively:
@(trig or enable) rega = regb; // controlled by trig or enable
@(posedge clk_a or posedge clk_b or trig) rega = regb;
The following examples show the use of the comma (,) as an event logical or operator:
always @(a, b, c, d, e)
always @(posedge clk, negedge rstn)
always @(a or b, c, d or e)