Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

The connection between channel depletion layer and SCE

Status
Not open for further replies.
S

sharas

Member level 4
Joined
Jun 7, 2005
Messages
74
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,286
Activity points
1,965
"The device with the thinner oxide has a smaller channel depletion layer and hence improved short channel charecteristic"

(Intel Technology Journal Q3'98/MOS Scaling: Transistor Challenges for the 21st Century, P.3 in the attached file)

Can anyone please explain this to me? How does the channel depletion layer size influence the SCE?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top