Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

The buffer amplifier affects the phase noise of PLL?

Status
Not open for further replies.
It will add on noise to the PLL circuit and therefore phase noise is degraded due to the buffer amplifier. The reason of having a buffer amplifier is to ensure it has sufficient isolation of PLL to other circuitry (ie. mixer or modulator).
 

How to calculate the effect of the buffer amp on the phase noise of PLL?
 

The noise added (SSB) will be N=FkT ; F buffer noise figure, k Boltzmann const, T temperature in kelvin
 

Yes...
A buffer amplifier will effect the phase noise behaviour of a VCO due to changing input impedance of this amplifier concerning of input signal level.
What it means ?
A signal which is sufficiently high will change the operating point of tha amplifier and this changing will impact the input impedance of that amplifier.

If input impedance is changed , the VCO will be impacted by this effect and it will return back as a phase noise.

Note that, I assume the signal level is sufficiently high to change the operating amplifier. Otherwise the noise that is added into noise figure of the system will be lower than this behaviour.

Second thing , phase noise is a random proccess and of course in the amplifier this noise will be added into signal.
But this is second degree effect..
 

In other word to reduce the added thermal noise select a low noise buffer, to reduce the pulling effect due the buffer input impedence variation use a VCO configuration not sensible to the pulling effect such as a common collector architecture or use matching pad.
 

I have a question . if PA output inpedance no matching, the VCO could be affected, cause he phase noise larger?
 

I think the mismatch may pull down the output power and it affects the noise of whole source when it changes the noise of PA.
 

Hi, mckinson: What are you trying to say? What do you meant by no impedance matching at PA output and VCO? This 2 components are not connected to each other usually.... Could you explain in detaiL?
 

Hi activewei. I've designed a mobile, the peak phase error at the first bit is very large about 15 degree.
My qusetion is that if the impedance PA output is no matching to the duplexer , the output signal reflected to VCO by the PA, cause the VCO frequency pulling
 

I do not understand what do you mean by"peak phase error at the first bit"? I am not very clear on your question but I think your concern is reflected signal at the output of PA. In fact, if there is any mismatching at the output of the PA, the PA will be the first victim (might lead to permanent device/chip damage). This problem can be minimized by adding an isolator after PA. As for VCO, to minimize the pulling effect, add attenuator (match to 50 ohm) as close as possible to the VCO output. For isolation, you can choose either adding buffer amplifier/isolator after attenuator to minimize the effect. My recent investigation shows that isolation of at least 30dB is necessary between the VCO to other circuit (i.e.mixer).
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top