Re: Scan chain balance
ok, thank you for the reply. So each scan chain is loaded simulataneously, usually thru I/O that support normal operation and scan mode (scan in/out). If each scan chain uses a set of test vectors, wouldn't the worst case scan "run time" be a factor of which scan chain requires the largest set of vectors? I don't see how Synopsys DFT Compiler would know how many vectors are generated in TetraMax.
Does anyone have any real world numbers as to how many scan chains you would have on, say, a 100 million gate chip?
What was the maximum scan chain size supported by the vendor (if there was one)?
How many total vectors were required?
Regards.