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Hi,
if your scan chain length is not uniform i.e. varies with more than 50 flops ,,, then there is no issue ,,but it is not recomemded as the tool will generate patterns with respect to the longest chain... so simulation time will increase because of extra pattens which are not used by small chains.You can easily avoid the diffenences in chain length.
I'm not that familiar with DFT.....but, what do you do in the case where you have a large SoC that has various cores that have different scan chain lengths?
Balancing the scan chain is critical because if you have scan 10 scan chains and 9 chains has 10 flops but the 10th chain has 100 flops each shift has to be 100 clock pulses and unnecessarily the tool has to insert X for 90 clock cycles. so your overall test time for one pattern will be 100 clock cycles to scan in, 100 to scan out and one capture cycle. It could have been 10 to shift in, 10 to shift out and 1 capture cycle. so you overall test time for one pattern is 201 instead of 21. Now multiple this by the number of pattern's. on average in this scenario your test time is 10 times higher. Hope this explains your question.
1) What port are you using to shift the pattern in?
2) How do you select a single scan chain when you are shifting in/out?
3) Assuming you can select a scan chain, why can't a tester support varying sizes of scan chains?
1) What port are you using to shift the pattern in?
a) Scan in ports
2) How do you select a single scan chain when you are shifting in/out?
b) you cant. You total shift in time and shift out time equals your longest chain length.
3) Assuming you can select a scan chain, why can't a tester support varying sizes of scan chains?
a) Atleast as far as I know u cant select single scan chain. Assuming u r testing the same macro, it doesn't make sense testing each chain separately(In theory u can do that). For example
you have to first take one scan chain test it and then load the faults from that test, and do the same for all the chains. This is cumbersome and highly inefficient.
ok, thank you for the reply. So each scan chain is loaded simulataneously, usually thru I/O that support normal operation and scan mode (scan in/out). If each scan chain uses a set of test vectors, wouldn't the worst case scan "run time" be a factor of which scan chain requires the largest set of vectors? I don't see how Synopsys DFT Compiler would know how many vectors are generated in TetraMax.
Does anyone have any real world numbers as to how many scan chains you would have on, say, a 100 million gate chip?
What was the maximum scan chain size supported by the vendor (if there was one)?
How many total vectors were required?
--> If each scan chain uses a set of test vectors, wouldn't the worst case scan "run time" be a factor of which scan chain requires the largest set of vectors?
A) you are confused. Scan chain has nothing to do with the vectors. Scan chain is a factor number of FF in ur design. Vectors is a factor of amount of combo logic(i.e no. of faults in the design) and quality of the design.
--> I don't see how Synopsys DFT Compiler would know how many vectors are generated in TetraMax.
A) No it doesn't know. as above its a factor of total logic to test and quality of the design.
By quality I mean if you have loops and lot of reconverging ETC.. logic then the number of vector will shoot up.
--> Does anyone have any real world numbers as to how many scan chains you would have on, say, a 100 million gate chip?
What was the maximum scan chain size supported by the vendor (if there was one)?
How many total vectors were required?
a) don't have numbers.
I suggest u read Essentials of electronic testing for digital, memory, and mixed-signal VLSI by vishwani agrawal. It's a very good book.
Regards.[/QUOTE]
Bushnell & Agrawal say on page 473 that the scan test time (what I called "run time") is a factor of Nsff*Ncomb, where Nsff = Number of scan flip flops and Ncomb = Number of combinatorial test vectors. Thanks for the suggested book.
Generally 99.99 precent of test time (on the tester) is spent loading the scan chains and this is directly proportional to the length of the longest scan chain in your design. So the way to minimize test time is to minimize the length of your longest parallel chain.
Make all parallel chains the same length and maximize the number of parallel chains. There really is almost no overhead for using a pin as a scan inpin or outpin so use 1/2 for scan in and 1/2 for scan outs. Some pins can't be used as scan pins, but excluding those if your design has 400 pins then 200 parallel chains will provide maximum efficiency.
Some testers have a test head that provides memory efficient loading of a limited number of scan chains and you would not be able to use a test head with this number of chains. Just do broadside loading of the scan chains.
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