Testbench StateX

[KingMoshe]

Hi all,
I made a testbench to test my module and I see weird behavior.
please look at the signal INV_TURN_OFF and INV_TURN_OFF_N.
The relation between the two signals is: INV_TURN_OFF_N = ~INV_TURN_OFF.
I don't understand why the signal INV_TURN_OFF_N got value StX.

 

[FvM]

I suspect there are more drivers for INV_TURN_OFF_N. Show the full code.

In Modelsim, you have a track 'X' function.

 

[KingMoshe]

I suspect there are more drivers for INV_TURN_OFF_N. Show the full code.

In Modelsim, you have a track 'X' function.

Hi, There is no more drivers for INV_TURN_OFF_N

 

[KlausST]

Hi,

from the given simulation result, I agree with FvM ... and expect the problem in the (whole) code.

--> Show us the whole code, then we are able to find the problem.

Klaus

 

[KingMoshe]

Hi,
Sorry, you are right, I have more logic, so I will try to explain better:
This is the relation between INV_TURN_OFF to INV_TURN_OFF_S (S = synchronizer output)
The picture below taken from module that have into it the the sync module:

and the is the code:

always @ ( posedge clk )
    begin
        if (RST) temp <= SYNC_VAL ;
        else temp <= D ;
    end
      
always @ ( negedge clk )
    begin
        if (RST) Q <= SYNC_VAL ;
        else Q <= temp ;
    end

Now, I don't understand why I see the blue HiZ in the sync output.
If I simulate only the sync module the relation between input to output looks fine.
Here example to the sync module simulation:

 

[KlausST]

Hi,

what is "SYNC_VAL" .. and where is it defined?

Klaus

 

[KingMoshe]

please see:

---

Code Verilog - [expand]
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module SYNC_INPUT (D,
                    clk,
                    RST,
                    //output
                    Q
                    ) ;
 
parameter SYNC_VAL = 1'b0;    //a default value output during RST (immediately after RST)               
// Inputs
input wire D;
input wire clk;
input wire RST;
 
//Outputs
output reg Q ;
 
reg temp ;
 
 
always @ ( posedge clk )
    begin
        if (RST) temp <= SYNC_VAL ;
        else temp <= D ;
    end
   
   
always @ ( negedge clk )
    begin
        if (RST) Q <= SYNC_VAL ;
        else Q <= temp ;
    end

---

 

[KlausST]

Hi,

here a snippet, there a snippet...

you don´t do yourself a favour.

Klaus

 

[KingMoshe]

Hi,

here a snippet, there a snippet...

you don´t do yourself a favour.

Klaus

I tried to be the most focused and clear

The last one is the full code.

 

[FvM]

Your second and following posts have little to do with the original post. In the original post, INV_TURN_OFF_N is combinational, driven by assign statement.

Now you have clocked registers. How about the original problem, is it solved, or did you report it incorrectly?

As for the synchronizer in the last post, you should show the module instantiation with the respective test bench. But there's no instantiation of synchronizer in second post...

 

[dpaul]

@KingMoshe
There is a simple rule here....if you provide less or incomplete info, you get less or partial help!