Hi all,
I made a testbench to test my module and I see weird behavior.
please look at the signal INV_TURN_OFF and INV_TURN_OFF_N.
The relation between the two signals is: INV_TURN_OFF_N = ~INV_TURN_OFF.
I don't understand why the signal INV_TURN_OFF_N got value StX.
Hi,
Sorry, you are right, I have more logic, so I will try to explain better:
This is the relation between INV_TURN_OFF to INV_TURN_OFF_S (S = synchronizer output)
The picture below taken from module that have into it the the sync module:
and the is the code:
Code:
always @ ( posedge clk )
begin
if (RST) temp <= SYNC_VAL ;
else temp <= D ;
end
always @ ( negedge clk )
begin
if (RST) Q <= SYNC_VAL ;
else Q <= temp ;
end
Now, I don't understand why I see the blue HiZ in the sync output.
If I simulate only the sync module the relation between input to output looks fine.
Here example to the sync module simulation:
Your second and following posts have little to do with the original post. In the original post, INV_TURN_OFF_N is combinational, driven by assign statement.
Now you have clocked registers. How about the original problem, is it solved, or did you report it incorrectly?
As for the synchronizer in the last post, you should show the module instantiation with the respective test bench. But there's no instantiation of synchronizer in second post...