library ieee;
use ieee.std_logic_1164.all;
entity verify_neg_logic_flip_flop is
end entity verify_neg_logic_flip_flop;
architecture verify of verify_neg_logic_flip_flop is
signal d, clk, ce, pre, clr: std_logic;
signal q, q_n: std_logic;
begin
duv : entity work.flip_flop(behave)
port map (d => d,
clk => clk,
ce => ce,
pre => pre,
clr => clr,
q => q,
q_n => q_n);
--tmp_q => tmp_q);
apply_test_case: process is
begin
pre <= '1'; d <= '0'; wait for 1 sec;
pre <= '1'; d <= '1'; wait for 1 sec;
pre <= '0'; d <= '0'; wait for 1 sec;
pre <= '0'; d <= '0'; wait for 1 sec;
wait on clk until clk = '1';
clr <= '1'; d <= '0'; wait for 1 sec;
clr <= '1'; d <= '1'; wait for 1 sec;
clr <= '0'; d <= '0'; wait for 1 sec;
clr <= '0'; d <= '0'; wait for 1 sec;
wait on clk until clk = '1';
ce <= '1'; d <= '0'; wait for 1 sec;
ce <= '1'; d <= '1'; wait for 1 sec;
ce <= '0'; d <= '0'; wait for 1 sec;
ce <= '0'; d <= '0'; wait for 1 sec;
wait;
end process apply_test_case;
check_outputs: process is
begin
wait on pre, clr, clk, ce;
wait for 10 ms;
assert not (pre = '0' and clr = '0');
end process check_outputs;
end architecture verify;