test point insertion

[rajusripathi83]

hi,



how to find controllability and observability using dft compiler and tetramax.

 

[maulin sheth]

TetraMAX Tool itself calculates the controllability and observability.We can not see any type of report or log file for the calculation of Controllability and Observability.
But TetraMAX generates pattern w.r.t. its Controllability and Observability.

 

[rajusripathi83]

thank you sir,


1) if we want to see the controllability and observability values what we need to do? there is any way?

2)what are the inputs for tetramax? ans stil protocol file, scan stitched routed netlist, simulatiom libraries) is correct or not?

3) in tetramax there is two options simulation and fault simulation what is the diffarence between them , the atpg patterns are same for both or diffarent?

4)please can you tell the basic flow for tetramax?

5) The test points are added in tetramax or in dft compiler?

 

[maulin sheth]

1) I dont think any way to see the controllability and observability for the whole design.But we have a option like set_pindata in the TetraMAX through which we can get the controllability and observability.
2) Inputs of tetraMAX are correct.
3) Pl tell me the meaning of Simulation and Fault Simulation.
4) Have you a TetraMAX UG?thn u can get all this information.
5) We can not change/insert in netlist through TetraMAX.Because TetraMAX is just for the pattern Generation Purpose.For Inserting in the Design we have to use Design/DFT Compiler.

 

[rajusripathi83]

a) sir iam not understanding the diffarence, first we will do simulation at begining stage using (vcs) ,why we again simulating in tetramax.

coming to fault simulation we assume that the circuit is falty i,e by adding faults.

b) sir for inserting test points we can use the folloing flow

please help me

for test point insertion below flow is correct or not ?

1--take rtl and do functionl verification......input=rtl,tb output=functional simulation out put file

2--take the rtl into dft compiler run with required constraints & generate un mapped netlist ........input=rtl,library ,,,output=unmapprd netlist

3--insert dft (define ports)

4--generate scan ready netlist......input=unmapped netlist, output=scan ready netlist

5--generate scan stitched netlist........input=scan ready netlist, output=scan stitched netlist

6--create test protocol file

7-- do physical design implementation up to routing.....input to ic compiler=scan stitched netlist, output=routed scan stitched netlist

8--the routed scan stitched netlist, simulation library & protocol file are taken into tetramax.....i/p=routed scan stitched netlist,library,protocol file

9--do simulation, & fault simulation (doubt ::::how to do simulation and fault simulation and how we will compare)

10--find the undetected faults

11--find location of undetectable faults

12--analyze the results

13--for inserting user defined test points go to dft compiler (doubt::::::where we need to go step 2 or 3 or 4 or 5 or 6 or 7)

14--insert the test points

15--repeat the step 5 to step 12

- - - Updated - - -

a) sir iam not understanding the diffarence, first we will do simulation at begining stage using (vcs) ,why we again simulating in tetramax.

coming to fault simulation we assume that the circuit is falty i,e by adding faults.

b) sir for inserting test points we can use the folloing flow

please help me

for test point insertion below flow is correct or not ?

1--take rtl and do functionl verification......input=rtl,tb output=functional simulation out put file

2--take the rtl into dft compiler run with required constraints & generate un mapped netlist ........input=rtl,library ,,,output=unmapprd netlist

3--insert dft (define ports)

4--generate scan ready netlist......input=unmapped netlist, output=scan ready netlist

5--generate scan stitched netlist........input=scan ready netlist, output=scan stitched netlist

6--create test protocol file

7-- do physical design implementation up to routing.....input to ic compiler=scan stitched netlist, output=routed scan stitched netlist

8--the routed scan stitched netlist, simulation library & protocol file are taken into tetramax.....i/p=routed scan stitched netlist,library,protocol file

9--do simulation, & fault simulation (doubt ::::how to do simulation and fault simulation and how we will compare)

10--find the undetected faults

11--find location of undetectable faults

12--analyze the results

13--for inserting user defined test points go to dft compiler (doubt::::::where we need to go step 2 or 3 or 4 or 5 or 6 or 7)

14--insert the test points

15--repeat the step 5 to step 12