#### hemanth434

##### Newbie level 4

entity Encrypt is

Port ( rs1 : in STD_LOGIC_VECTOR (15 downto 0);

rs2 : in STD_LOGIC_VECTOR (15 downto 0);

rs3 : in STD_LOGIC_VECTOR (15 downto 0);

rs4 : in STD_LOGIC_VECTOR (15 downto 0);

k1,k2,k3,k4 : in STD_LOGIC_VECTOR (15 downto 0);

pt : in STD_LOGIC_VECTOR (15 downto 0);

LFSR : in STD_LOGIC_VECTOR (15 downto 0);

ct : out STD_LOGIC_VECTOR (15 downto 0));

end Encrypt;

architecture Behavioral of Encrypt is

signal x1,x2,x3,x4,x5 : std_logic_vector(15 downto 0);

signal v12,v23,v34 : std_logic_vector(15 downto 0);

signal rs1_ext : std_logic_vector(15 downto 0);

signal rs2_ext : std_logic_vector(15 downto 0);

signal rs3_ext : std_logic_vector(15 downto 0);

signal rs4_ext : std_logic_vector(15 downto 0);

begin

process(rs1,rs2,rs3,rs4,pt,k1,k2,k3,k4,LFSR)

variable i : integer;

begin

for i in 0 to 3 loop

x1 <= rs1 + pt;

v12 <= x1 xor k1;

x2 <= v12+ rs2_ext;

v23 <= x2 xor k2;

x3 <= v23 + rs3_ext;

v34 <= x3 xor k3;

x4 <= v34 + rs4_ext;

ct <= x4 xor k4;

rs1_ext <= rs1_ext + v34;

x1 <= v23 + LFSR;

rs3_ext <= rs3_ext + x1;

x2 <= v12 + rs1_ext;

rs4_ext <= rs4_ext + x2;

x3 <= v12 + rs4_ext;

rs2_ext <= rs2_ext + x3;

end loop;

end process;

end Behavioral;

plse giv the solution to my problem