Test bench for simple Register file

Code Verilog - [expand]
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// 16 x 32 register file with two read, 1 write port
 module regfile(
        input  logic    clk, we3,
        input  logic    [31:0] a1, a2, a3,
        input  logic     [31:0] wd3,
        output logic    [31:0] rd1, rd2);
 
logic  [31:0] RAM[15:0];   //16 regsiters
 
assign rd1 = RAM[a1];  // asynchronous read
assign rd2 = RAM[a2];
 
always @(posedge clk)
 begin  // synchronous write
if (we3)
    RAM[a3] <= wd3;
 end     
 endmodule

Code Verilog - [expand]
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module regfile_tb();
      logic    clk=0, we3;
      logic    [31:0] a1, a2, a3;
      logic     [31:0] wd3;
     logic    [31:0] rd1, rd2;
 
 regfile uut(.clk(clk), .we3(we3), .a1(a1), .a2(a2), .a3(a3),   
 .wd3(wd3), .rd1(rd1), .rd2(rd2));
 
always  #5 clk = ~clk; 
initial begin
#2 
we3=1;
a1=4;
a2=5;
wd3=15;
a3=15;
#10 $finish;
end
endmodule