library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_tb is
end adder_tb;
architecture adder_16b of adder_tb is
component adder
port(
a : in std_logic_vector (15 downto 0);
b : in std_logic_vector (15 downto 0);
s : out std_logic_vector (15 downto 0);
cf : out std_logic;
ovf : out std_logic
);
end component;
signal a : std_logic_vector (15 downto 0):= "0000000000000000";
signal b : std_logic_vector (15 downto 0):= "0000000000000000";
signal s : std_logic_vector (15 downto 0):= "0000000000000000";
signal cf : std_logic := '0';
signal ovf : std_logic := '0';
begin
UUT: adder port map (a=>a, b=>b, s=>s, cf=>cf, ovf=>ovf);
adder_pro:process
begin
a<="0000000000000000"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000001"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000010"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000011"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000100"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000101"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000110"; b<="0000000000000000"; wait for 10ns;
a<="0000000000000111"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001000"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001001"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001010"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001011"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001100"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001101"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001110"; b<="0000000000000000"; wait for 10ns;
a<="0000000000001111"; b<="0000000000000000"; wait for 10ns;
wait;
end process;
end;