Test Bench Code for Reset

[sunidrak]

Hi

I have a test bench for some DUT, In that this code is written

initial
begin
RESET = 'b1;
#10 RESET = 'b0;
#10 @(posedge clk)
RESET = 'b1;
end

can any body please explain the use of #10 @(posedge clk) line ?
Does it mean to apply the reset for at-least 1 clk cycle ?

Regards
SUNIL

 

[mail4idle2]

We are making sure the reset (removal) and clock pos edge does not come at the same time.

 

[dave_59]

Actually, this code makes sure the reset removal occurs in a race with the posedge clock.

Without seeing the clk generation, all you can say is that reset is applied at time 0, waits 10 time units, then waits for a posedge of clk, then removes reset. So the only thing you can say for certain is that reset will be applied for at least the first 10 time units of simulation.

 

[sunidrak]

Actually, this code makes sure the reset removal occurs in a race with the posedge clock.

Without seeing the clk generation, all you can say is that reset is applied at time 0, waits 10 time units, then waits for a posedge of clk, then removes reset. So the only thing you can say for certain is that reset will be applied for at least the first 10 time units of simulation.

Thank you so much Sir