imhiya
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Hello,
Just was hoping someone should shine some light on my issue, or give me the correct angle.
Basically, (in theory) I have a 12 bit A/D Temp sensor, this gives a natural bit output ranging from 0 to 4096, -50c to 200c
This is fed into a temp convertor to make it into fahrenheit.
To convert it to fahrenheit, we are given the equation,
Tf approx = ((1.75 * Tc) + 32)
The issue I'm having is, the output of the temp convertor, needs to be 12 bit SIGNED, so ranging from -2048 to 2048. So my problem comes where, I need to convert the input from unsigned to signed, and I've also realised that if a value over 2322 from the A/D temp is fed in, then it will cause the output to be all 1's.
So what is my bed approach, I'll attach my current code.
Just was hoping someone should shine some light on my issue, or give me the correct angle.
Basically, (in theory) I have a 12 bit A/D Temp sensor, this gives a natural bit output ranging from 0 to 4096, -50c to 200c
This is fed into a temp convertor to make it into fahrenheit.
To convert it to fahrenheit, we are given the equation,
Tf approx = ((1.75 * Tc) + 32)
The issue I'm having is, the output of the temp convertor, needs to be 12 bit SIGNED, so ranging from -2048 to 2048. So my problem comes where, I need to convert the input from unsigned to signed, and I've also realised that if a value over 2322 from the A/D temp is fed in, then it will cause the output to be all 1's.
So what is my bed approach, I'll attach my current code.
Code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.ALL;
entity TC_12bit is
port ( CENT_in : in STD_LOGIC_VECTOR(11 downto 0);
FAH_out : out STD_LOGIC_VECTOR(11 downto 0));
end TC_12bit;
architecture behavioural of TC_12bit is
signal Tc : STD_LOGIC_VECTOR(11 downto 0);
signal Tc_shift_r_1 : STD_LOGIC_VECTOR(11 downto 0);
signal Tc_shift_r_2 : STD_LOGIC_VECTOR(11 downto 0);
begin
Tc <= CENT_in;
Tc_shift_r_1(10 downto 0) <= CENT_in(11 downto 1);
Tc_shift_r_1(11) <= CENT_in(11);
Tc_shift_r_2(9 downto 0) <= CENT_in(11 downto 2);
Tc_shift_r_2(11) <= CENT_in(11);
Tc_shift_r_2(10) <= '0';
FAH_out <= std_logic_vector(signed(Tc) + signed(Tc_shift_r_1) + signed(Tc_shift_r_2) + 32);
end behavioural;