Taping out with WNS..

[vijayatmu]

hello all,

Is it common in first maskset to tapeout with some WNS on some of the paths? WIll you still signoff STA as ok and go ahead with tapeout.

I understand this depends on the design and how conservative various design constraints are setup, etc etc.

But if the timing constraints and clock are setup very aggressive, it is likely to fail. If the WNS is 1-2% of the clock period, do you think it is ok.

The reason I ask this Q is because my product got tapedout with some marginal WNS. When I checked with the project lead he said those are usually ok when the silicon comes out.

Let me know your thoughts.

Thanks.

 

[lostinxlation]

I have taped out some chips with a small setup violations. I even taped out one chip with a small hold viols as well. But we were super hurry to tapeout for some business reason and took a risk.
Usually, the chip doesn't run at the worst condition which the timing lib is characterized with and it works at the target clock speed most of the time if the viols from STA is tiny. But if it deosn't work, you'll regret so we usually try to pass it with a target clock speed, though.

 

[brs2k4]

We have taped-out with few (2-3ps) setup and hold slack but the violations are in non-critical corners (like Slow-Slow setup mode or Slow-Slow hold mode with worst-RCs etc.). Also at times when the violations are in Scan mode.

But we need to ensure we have clean timing in the 'all critical' functional modes!