In the design which i'm working on, there are several macros. And due to insufficient spacing between two macros vertical edges the tapcells were wrongly plaed. And these tap cells are overlapping VSS stripe.
What is the issue caused due to this overlap, like any DRCs? Is there any exception for VDD power stripe ?
this won't cause DRCs per se, but will most likely yield a poor utilization. standard cells do not like to be placed under stripes, routing resources are scarce there.