thank you for your answers.
can you explain more about the testbench of passive mixer for this(input impedance simulation) by pss+pac. how do i have to do it? what is the conditions of lo and rf ports in this simulation. are the lo port grounded? and what is the pss+pac windows conditions?
I am sorry.I had a mistake. the 900ohm was my lna output impedance and my frequency is 2.4G.I have changed the l &c of my lc(not rlc) tank to 3.62nH and 890fF respectively.the output impedance of my cascode common source lna is 500 ohm now but the q decreases a little. how much value of q is practical for on chip implimentation of lc tank.you consider this problem that i have too small area for my lna, on chip.(.21mm2 for an lna with 12nH, 3.6nH , .8nH , caps and three lare transistors and two i and q mixers i.e. the whole of front-end!!)is it possible to implement all of them in such an small area?!