archillios
Full Member level 1
hi everybody!
I was puzzled by power-on-sequence problem now.
I used to do a project using smic 130nm logic technology, using its standard io lib.
SMIC demand io power first, core power second sequence.
The reason behind this rule is ESD Diode between io power ring and core power ring in IO Cell circuit.
But, When I turn to TSMC tech, I find different rule, TSMC consider power on sequence only in IO Crowbar current, do not care ESD diode at all!
Why?
Who has TSMC power on sequence experience, can you share some idea on it?
Thanks!
I was puzzled by power-on-sequence problem now.
I used to do a project using smic 130nm logic technology, using its standard io lib.
SMIC demand io power first, core power second sequence.
The reason behind this rule is ESD Diode between io power ring and core power ring in IO Cell circuit.
But, When I turn to TSMC tech, I find different rule, TSMC consider power on sequence only in IO Crowbar current, do not care ESD diode at all!
Why?
Who has TSMC power on sequence experience, can you share some idea on it?
Thanks!