T flipflop code problem (VHDL)

[makanaky]

I was designing T flipflop , I wrote the following code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TFF is
Port ( reset : in STD_LOGIC;
enable : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC);
end TFF;

architecture Behavioral of TFF is
signal A:std_logic:='0';
begin
process (clk,reset)
begin
if reset='1' then
Q<='0';
elsif rising_edge(clk) then
if enable='1' then
A<= not A;

end if;
end if;

end process;

Q<= A;
end Behavioral;

problem is when simulating : Q doesnt get to '1' when A changes to '1' , instead it becomes dont care 'X'

Can anybody help me please why does this happen ?

 

[TrickyDicky]

you have Q driven from inside the process and outside the process, so it will always be 'X'. Remove Q from the reset condition and replace it with A. Q is not a register output, A is. Q is just a wire here.

 

[makanaky]

Thanks a lot . I replaced Q by A in the reset , but I got this half cycle delay between A and Q as shown . I dont understand why ???

Can you please explain ?

**broken link removed**

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[FvM]

There's no delay implemented in the logic. I guess, you have a simulation time step of 1 ns and are driving the design with a 2 ns clock period. Decrease the clock frequency or use a smaller timestep.

 

[makanaky]

where can i change the simulation time step in modelsim ? Anyway , I made the clk frequency 20 times smaller , and same result happens ...

 

[FvM]

where can i change the simulation time step in modelsim

[vsim]
Resolution = xx

The waveform doesn't fit the code, I think. The waveform looks like Q <= A is placed inside the process.

 

[makanaky]

Thanks a lot FVM , That's right , Q <= A was inside the process as I was making changes to see what could this change in the o/p

Can u plz explain why when Q<=A was inside the process , this o/p appeared ?

 

[FvM]

The behaviour is due to VHDL specification, that the left hand side of expressions in a process is only updated according to the sensitivity list. This only happens in simulation, so having signals missing in the sensitivity list leads to a simulation to hardware mismatch.

The assignments in the clock synchronous block under if rising_edg(clk) don't need to appear in the sensitivity list however.

 

[makanaky]

this means if i included A in sensitivity list , the o/p would be correct with Q<=A inside the process ?

 

[TrickyDicky]

this means if i included A in sensitivity list , the o/p would be correct with Q<=A inside the process ?

Not if its inside the clocked part of the process, because even if A changes, there is no clock edge, so Q will not change.

Sensitivity lists are only important if you have an unclocked process. Writing a line of code outside of an explicit process creates an implicit process with an impied sensitivity list.
eg.

Q <= A;

is implied as:

process(A)
begin
Q <= A;
end process;

 

[makanaky]

thanks a lot guys