SystemVerolog Problem with VCS

[aspirinnnnn]

I had this code downloaded from internet ,and I want to run it with VCS ,but encounter such error:

Error-[INIPL] Identifier not in port list
Identifier 'ha_if' does not appear in port list.
"half_adder_if.sv", 23
Source info: half_adder_if ha_if;

the original code is shown below:

`ifndef _HALF_ADDER_IF_SV_
`define _HALF_ADDER_IF_SV_
interface half_adder_if;
	logic a,b;
	logic sum;
	logic carry;
endinterface 

module half_adder(half_adder_if ha_if);
	assign ha_if.sum	=	ha_if.a ^ ha_if.b;
	assign ha_if.carray =	ha_if.b & ha_if.b;
endmodule

module tb;
	logic clk;
	half_adder_if ha_if;
	half_adder u1(.ha_if(ha_if));

	initial begin
		clk=1;
		forever #10 clk=~clk;
	end
	initial begin
		ha_if.a<=0;ha_if.b<=0;
		@(posedge clk) ha_if.a =0 ; ha_if.b=1;
		@(posedge clk) ha_if.a =1 ; ha_if.b=0;
		@(posedge clk) ha_if.a =1 ; ha_if.b=1;
		@(posedge clk) $finish;
	end

endmodule




`endif

This seems a rather simple example, i don't know where went wrong
I run it with the following comand :

VCS +v2k -severilog -debug_all half_adder_if.sv

 

[tariq786]

why dont you switch to verilog instead of system verilog and then try to compile. I dont see any advantage using system verilog to test an adder.

 

[aspirinnnnn]

I am learning systemverilog ,so I started with a simple one.
BTW, I found where i was wrong. the Instantiation of the interface should wrote like :

half_adder_if ha_if();

but not

]half_adder_if ha_if