systemverilog testbench connection with DUT thru interface

[ebuddy]

I defined a fifo interface:

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Code Verilog - [expand]
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interface fifoint ();
  logic clk;
  logic rstn;
  logic [3:0] cin;
  logic [3:0] cout;
  
  modport dut (input clk, rstn, cin, output cout);
  modport tb (input clk, rstn, cout, input cin);
  
endinterface

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And my DUT looks like this:

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Code Verilog - [expand]
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module fifo (input clk, rstn, input [3:0] cin, output reg [3:0] cout);
   .....  
endmodule

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So when I am trying to connect dut in the testbench, I will do this:

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Code Verilog - [expand]
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module t_fifo ();
 
  fifoint mfifoint();
  
  tp i_tp(mfifoint.tb);
 
  fifo dut (
    .clk (mfifoint.dut.clk),
    .rstn (mfifoint.dut.rstn),
    .cin (mfifoint.dut.cin),
    .cout (mfifoint.dut.cout)
  );
 
endmodule

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Modelsim just complains that "A modport ('dut') should not be used in a hierarchical path"

What is other way to write this and avoid any warnings?

 

[dave_59]

Modports are only used in interface port and virtual interface declarations. They are not used to reference individual interface items.

A hierarchical reference into an interface instance works the same as a hierarchical reference to a module instance. So just write

 fifo dut (
    .clk (mfifoint.clk),
    .rstn (mfifoint.rstn),
    .cin (mfifoint.cin),
    .cout (mfifoint.cout)
  );