Systemverilog interface Question

[aspirinnnnn]

I have a interface like

interface mAHB_bus
	#(
		parameter SLAVE_NUM=8
	);
	logic	[SLAVE_NUM-1:0]	slave_wren;
	logic	[1:0]			slave_size;
	logic	[15:0]			slave_wraddr;	
	logic	[31:0]			slave_wrdata;
	logic	[SLAVE_NUM-1:0]	slave_rden;
	logic	[15:0]			slave_rdaddr;

	modport bus(
		output	slave_wren,
		output	slave_size,
		output	slave_wraddr,
		output	slave_wrdata,
		output	slave_rden,
		output	slave_rdaddr
	);	
		
	modport slave0(
		input	slave_wren[0],
		input	slave_size,
		input	slave_wraddr,
		input	slave_wrdata,
		input	slave_rden,
		input	slave_rdaddr
	);

        modport slave1(
		input	slave_wren[1],
		input	slave_size,
		input	slave_wraddr,
		input	slave_wrdata,
		input	slave_rden,
		input	slave_rdaddr
	);

but it seems that the slave_wren[0] and slave_wren[1] parts won't compile, wonder why?
if this is wrong , how can i work it around

 

[dave_59]

You can use something called a modport expression, which is similar to a Verilog module port expression. By default, port names are created using the same name as the signal it is connected to, but you are not allowed to have selects in port names. So you can do

interface mAHB_bus
	#(
		parameter SLAVE_NUM=8
	);
	logic	[SLAVE_NUM-1:0]	slave_wren;
	logic	[1:0]			slave_size;
	logic	[15:0]			slave_wraddr;	
	logic	[31:0]			slave_wrdata;
	logic	[SLAVE_NUM-1:0]	slave_rden;
	logic	[15:0]			slave_rdaddr;

	modport bus(
		output	slave_wren,
		output	slave_size,
		output	slave_wraddr,
		output	slave_wrdata,
		output	slave_rden,
		output	slave_rdaddr
	);	
		
	modport slave0(
		input	.slave_wren(slave_wren[0]),
		input	slave_size,
		input	slave_wraddr,
		input	slave_wrdata,
		input	slave_rden,
		input	slave_rdaddr
	);

        modport slave1(
		input	.slave_wren(slave_wren[1]),
		input	slave_size,
		input	slave_wraddr,
		input	slave_wrdata,
		input	slave_rden,
		input	slave_rdaddr
	);

From inside the module using the slave0 and slave1 modport, you would just reference the name slave_wren.
This is an obscure feature. Make sure your simulation and synthesis tools support this syntax.

 

[aspirinnnnn]

thanks very much, and I figured why i was wrong ,if I using the slave_wren[0] or slave_wren[1] in the modport, it is impossible to reference it in another module with the same interface, I can't refer a signal as slave_wren[0].

and actually I want to ask you one more question Sir, since I have been working on a relative complex project, and will continue on this project in the next two years , i figured it will be good for me to do the verification in the future, but I am the only man power I got, I don't know how much work and how long it takes to build a good layered testbench as described in the 'SystemVerilog for Verification ' book?

 

[dave_59]

That's why we have the UVM. It's a standard way of assembling a layered testbench. See https://verificationacademy.com/ for a lot more information.

 

[aspirinnnnn]

I found that VCS don't support for this feature, is there any way i can work around this ?

- - - Updated - - -

You can use something called a modport expression, which is similar to a Verilog module port expression. By default, port names are created using the same name as the signal it is connected to, but you are not allowed to have selects in port names. So you can do

interface mAHB_bus
	#(
		parameter SLAVE_NUM=8
	);
	logic	[SLAVE_NUM-1:0]	slave_wren;
	logic	[1:0]			slave_size;
	logic	[15:0]			slave_wraddr;	
	logic	[31:0]			slave_wrdata;
	logic	[SLAVE_NUM-1:0]	slave_rden;
	logic	[15:0]			slave_rdaddr;

	modport bus(
		output	slave_wren,
		output	slave_size,
		output	slave_wraddr,
		output	slave_wrdata,
		output	slave_rden,
		output	slave_rdaddr
	);	
		
	modport slave0(
		input	.slave_wren(slave_wren[0]),
		input	slave_size,
		input	slave_wraddr,
		input	slave_wrdata,
		input	slave_rden,
		input	slave_rdaddr
	);

        modport slave1(
		input	.slave_wren(slave_wren[1]),
		input	slave_size,
		input	slave_wraddr,
		input	slave_wrdata,
		input	slave_rden,
		input	slave_rdaddr
	);

From inside the module using the slave0 and slave1 modport, you would just reference the name slave_wren.
This is an obscure feature. Make sure your simulation and synthesis tools support this syntax.

I found that the VCS is not support this feature, is there any way i can work out this?? thanks a lot

 

[dave_59]

I found that VCS don't support for this feature, is there any way i can work around this

Yes, you could try Questa.

But maybe you don't need to use a modport.