dpaul
Advanced Member level 5
Hi,
I want to use the SysWip AXI4Lite Slave verification IP (in SystemVerilog) in my top-level test-bench with my traditional *Verilog* AXI4Lite master.
Being completely new to SystemVerilog, I have problems to port-map in the toplevel testbench.
What I have: From the SysWip I have downloaded axi4lite_s_if.sv which is an *interface* and the axi4lite_s.sv which is a *package* (http://syswip.com/axi4-lite-verification-ip).
From my legacy code I have a dut_top.v and dut_top_tb.sv (I have renamed it to .sv in order to support some SV constructs - import, creating the slave class object, etc). The Verilog AXI4Lite master module is instiantiated in the dut_top.v
Target: I want to connect the ports of the legacy Verilog AXI4Lite Master to that of the SysWip VIP slave. I am getting a Syntax error message where the ports are being mapped in the dut_top_tb.sv.
Of course I am doing it wrong, so please help me to rectify the mistake.
An excerpt from the dut_top_tb.sv is given below where the error is occuring. Note that I don't want to bring out the AXI4Lite master ports from the dut_top.v and so I am using the following way to connect the ports in the test-bench with the slave VIP BFM.
I want to use the SysWip AXI4Lite Slave verification IP (in SystemVerilog) in my top-level test-bench with my traditional *Verilog* AXI4Lite master.
Being completely new to SystemVerilog, I have problems to port-map in the toplevel testbench.
What I have: From the SysWip I have downloaded axi4lite_s_if.sv which is an *interface* and the axi4lite_s.sv which is a *package* (http://syswip.com/axi4-lite-verification-ip).
From my legacy code I have a dut_top.v and dut_top_tb.sv (I have renamed it to .sv in order to support some SV constructs - import, creating the slave class object, etc). The Verilog AXI4Lite master module is instiantiated in the dut_top.v
Target: I want to connect the ports of the legacy Verilog AXI4Lite Master to that of the SysWip VIP slave. I am getting a Syntax error message where the ports are being mapped in the dut_top_tb.sv.
Of course I am doing it wrong, so please help me to rectify the mistake.
An excerpt from the dut_top_tb.sv is given below where the error is occuring. Note that I don't want to bring out the AXI4Lite master ports from the dut_top.v and so I am using the following way to connect the ports in the test-bench with the slave VIP BFM.
Code:
.
. /////////////////////////////////////////////////////////////////////////////
// AXI4Lite VIP instance
/////////////////////////////////////////////////////////////////////////////
`ifdef AXI4LITE_VIP_syswip
axi4lite_s_if axi4lite_s_if_inst(); // create an instance for the SysWip interface
// ----------------------------------------------------------------------------
// AXI4-Lite Master signals connected to axi4lite_s_if
// ----------------------------------------------------------------------------
// READ address/cmd channel
te0630_top_inst.emi2axi4_lite_inst.m_AXI_AR_ADDR_o (axi4lite_s_if_inst.araddr);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_AR_VALID_o (axi4lite_s_if_inst.arvalid);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_AR_READY_i (axi4lite_s_if_inst.arready);
// READ data/response channel
te0630_top_inst.emi2axi4_lite_inst.m_AXI_R_DATA_i (axi4lite_s_if_inst.rdata[32:0]);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_R_RESP_i (axi4lite_s_if_inst.rresp);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_R_VALID_i (axi4lite_s_if_inst.rvalid);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_R_READY_o (axi4lite_s_if_inst.rready);
// WRITE address/cmd channel
te0630_top_inst.emi2axi4_lite_inst.m_AXI_AW_ADDR_o (axi4lite_s_if_inst.awaddr);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_AW_VALID_o (axi4lite_s_if_inst.awvalid);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_AW_READY_i (axi4lite_s_if_inst.awready);
// WRITE data channel
te0630_top_inst.emi2axi4_lite_inst.m_AXI_W_DATA_o (axi4lite_s_if_inst.wdata[32:0]);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_W_STRB_o (axi4lite_s_if_inst.wstrb[3:0]);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_W_VALID_o (axi4lite_s_if_inst.wvalid);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_W_READY_i (axi4lite_s_if_inst.wready);
// WRITE response channel
te0630_top_inst.emi2axi4_lite_inst.m_AXI_B_RESP_i (axi4lite_s_if_inst.bresp);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_B_VALID_i (axi4lite_s_if_inst.bvalid);
te0630_top_inst.emi2axi4_lite_inst.m_AXI_B_READY_o (axi4lite_s_if_inst.bready);
initial begin
// Create AXI4Lite_s_env class object
AXI4Lite_s_env_s_env axi4lite = new(axi4lite_s, axi4lite_s_if_inst, 4);
// Start AXI4-Lite Slave Environment
axi4lite.startEnv();
end
`endif
.
.
Last edited: