The only thing I see that is SV is the use of logic. What's the point? Other than that everything else will compile as standard Verilog.
Also I have a issue with using defines for things like the following:
Code:
`define FIFO_DEPTH 32
`define IN_BUS_WIDTH 5
`define FIFO_CNT_WIDTH 5
What if I have 6 FIFOs, that are all different sizes?
Haven't you ever done any
real design reuse code? These should all be parameters not defines, defines should never be used in synthesizable code unless it's used to select mutually exclusive options that change the design for say different product families or enable simulation only code. I also typically use them as the design's version/id code. Even then you still might want to avoid using them altogether as they are GLOBAL.
As most FPGA vendor tools now allow defining the top level parameters/generics in the compilation scripts/gui you can avoid using any kind of defines or such in your code even for the above mentioned uses. Though I typically use a script to generate a single version file that gets used during compilation, so that script normally gets automatically called each time the build process is run.
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Oh, besides what I've already mentioned, I don't think your design can handle a simultaneous read and write. Only the read will occur and the write gets ignored.