Continue to Site

# SystemVerilog Clocking Block

Status
Not open for further replies.

#### MarkMiller

##### Newbie level 1
initial clk = 1'b0;

forever #5 clk = ~clk;

default clocking cb @ (posedge clk);
endclocking

========================================

At t=0, clk = 0
At t=5, clk = 1
At t=10, clk = 0
At t=15, clk = 1
...

At t=0, what is cb
At t=5, what is cb
At t=10, what is cb
...

What is the frequency of cb?

##10 is 10 clock cycle of cb

What is the difference between
repeat (10) @(clk)
repeat (10) @(cb)

The frequency of cb will inversely propositional to the time unit of the module or block. If the time until is 1ns, then the frequency of clk is 100MHz, hence triggering/sampling of the cb block occurs at every 10ns. That is because "posedge clk" is used as the clocking event.

When you use something like "##10", you are actually saying wait for 10 clocking block events, which in this case is 10 'posedge clk'. That makes all of the following same (at least in this case -- timing wise):
Code:
repeat (10) @(cb);
##10;
repeat(10) @(posedge clk);

In the case of "repeat (10) @(clk)" (wait for 10 (either positive or negative) edges of clk), it is the half of "repeat (10) @(cb)" (wait for 10 posedges of clk).

keith1200rs

Points: 2