SystemC will die? Why, can anybody give an explain?

[bigrice911]

wesam gobran+ ieee

Years ago lot of people said systemC would be the perfect replacement of VHDL & verilog and it's gonna to be next generation efficient HDL. However till now, SystemC has not been in the HDL stage even as a minor role.

Synopsys declared that they would abandon SystemC EDA software development.

All attempts on SystemC proved to be an abortion? :?:

 

[yeewang]

2 reasons I think:
1. SystemC can't represent HW nature quite well and clearly.
2. SystemVerilog and other languages are emerging.

 

[saho]

i don't think so.

SystemC will be for System level modelling (transactional level model) and synthesis (Forte Design's Cynthesizer, Coware, Mentor Graphics). Sounds like to the evolution path that VHDL went through. as you know, VHDL had initially designed for simulation.

SystemC simulation supports are available from
1. modelsim 5.8 (version 6.0 has SystemC ported to Windows version)
2. Visual Elite
3. Aldec Riviera
4. Celoxica
5. Cadence
....

At the RTL level, HDLs are the best. So, verilog (systemverilog) and VHDL (version 200X) will be used.

look at the following paper by G. Martin from cadence. (the chart!)

 

[roger]

Have any comapny start to use systemC as HDL or modeling language?
what's the current status of the language. Has IEEE recongize it?

 

[sandusty]

Sony in the silicon valley used SystemC around 1998 and finished their project.

 

[seasonyangd]

I dont think SystemC is very good as a verification or HDL language. As I know, many company used for system modeling.

 

[Richardlin0301]

My friend in " synopsys " says , system C does not have a good prospect .

 

[kinysh]

Yes, Me too.
I heard from synopsys sales that system-C is not good.
Maybe it is a synopsys business trick. Because now they are pushing systemverilog.

 

[tohji]

SystemC is good for system design.
We just had the systemc to design a huge communication system.
It is very efficient and the best of all, it can be done by system guys.

Now you can co-simulate systemc with SPW and port your exiting design from SPW to systemc.

 

[tohji]

Just heard Coware got the SPW team from Cadance. Recently, system C got really sucessful. I am looking for some window based systemc simulator with hardware awear tools. Anybody has a clue?

 

[kidman]

I think SystemC is good, while I have no idea of SystemVerilog.

Synopsys has been pushing SystemVerilog to be an IEEE standard for a while, now it is. So Synopsys can declare abandon of SystemC.

Cadence Incisive provides good supports of SystemC. Novas is also providing interfaces to dumping SystemC signals to FSDB format.

I believe SystemC can model anything SystemVerilog can model. So it is not a language difference, if the simulation engine for such high level language is same as HDL's. It's your favorite.

 

[ram]

I am a strong supporter of systemC. I think that it will not die for at least for next 6-7 years. It has a strong feature of creating TLMs which can also be reused in testbanches

 

[baso4hao]

Now in my project,the system specification from system designer is in SystemC, and we need implement it in HDL,i think both design languages are useful for different design level.

 

[guox2]

The SystemC is not good as the expected at the beginning of the years. So it will be replaced by a new language, such as SystemVerilog, e-language or Jeda.

 

[daniel@2004]

cadence guys said systemC is strong in verification

 

[tutx]

In my opinion, SystemC will be strong in 5-10 years. Now, some tools support systemC 2.0 such as Modelsim,....

And we know that SystemC performs quickly and strongly in system level modeling.

 

[zhangpengyu]

systemc synthesis is not well support,
but it's powerful to system modeling.

 

[haoboy]

it is also useful for hardware-software Co-design.

 

[oxford]

I also support SystemC, now many EDA vendors release tools to
run it.

 

[nanako]

systemC is only suited for modelling purposes and now with the emerging of systemverilog, it will replace systemC completely as with systemC you still need a PLI to run with your RTL. On the other hand with Systemverilog, everything is under one family.