SystemC versus SystemVerilog

[jimjim2k]

Hi

This is a simple question:

Is there any superior performance of SystemC over SystemVerilog or vice versa?

IN THE WORLD OF MULTI-DICIPLINARY PROGRAMMING TOOLS AND APPROACHES, WHICH THE SYMBIOSYS OF THE SYSTEMS, ARCHITECTURES AND APPLICATIOSN GO TO BE MORE REALISTIC THAN EVER,..
WHAT DID YOU THINK ABOUT THE FUTHER OF SYSTEMC AND SYSTEMVERILOG?

IS IT CORRECT TO ASK ABOUT THE MAJORITY OF EACH ONE OVER THE OTHER?

I think there is a steady state point that implies the existance of both systemC and systemverilog beside of good conversion tools like X-Tek X-HDL.



tnx

 

[omara007]

I guess the main aspects of SystemVerilog over SystemC is that it's more predictability to be synthesizable in the near future .. while there are many obstacles on building a reliable logic synthesis tool for SystemC ..
Hence, SystemVerilog can compose a straight forword flow from systel-level design to GDSII .. while for SystemC, u need to re-invent the wheel once ur done from the system-level to RTL ..
The good thing about SystemC is that the big companies driving force behind it is huge .. so, it came to market with many supported good tools .. specially that it's based on C++ .. and we all know that GCC is a real professional free tool .. at the same time u can't find similar tool for SystemVerilog ..

 

[jjww110]

systemc is suitable for model, and systemverilog is combined verification with design language

 

[omara007]

Hint :
SystemVerilog is having a workshop in the current Design Automation Conference in Santa Clara in the coming couple of days ..