omara007
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omara007 said:Good manaman ..
but we will still be putting the system-level code in the trash can after done with verification! .. in other words, the code won't propagate from System Level to RTL if we are going to use SystemC for system-level and Verilog for RTL .. which means we will still be wasting the code ..
in verilog RTL we start from the beginging again .. but if we managed to write SystemC RTL with good synthesis .. then the won't need to start from the beginging again .. no need to re-invent the wheel ..
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