SystemC to GDSII !is it a dream?

[omara007]

synopsys systemc compiler discontinued

Hi folks ..
Is there a complete stable flow to start your design with SystemC for system-level modeling through SystemC for RTL , and get your RTL (how complecated it is) synthesized maturely, then go for the back end till GDSII ?

In other words .. if I started with SystemC (for system description) to design a WLAN chip for exmple, will I be forced to switch to VHDL/Verilog for RTL ? ..

 

[Sparc]

systemc for synthesis books

It's no more a dream but to gain actual maturity for SystemC to GDSII will take quiet some time. But if you are good at mixing Tool Design flow from different vendors. It is still possible.

 

[funzero]

systemc model of dram

I think , System C to RTL may be a good style to design , and rtl to GdsII is another question.

 

[AlexWan]

how to translate systemc code to rtl

Hi, omara007

Magma will release a tool: VLSI Compiler. But it only support the flow from RTL to GDSII in one-pass.

There are some obstacles from SystemC to GDSII.

Good Luck

 

[rprince006]

use systemc in writing rtl code

Yes, it is a dream. May be possible only for smaller designs. I don't think it can be
used to design a complex ASIC as processor or DSP. Because it is a system-level
language, you cannot use it to define architecture, pipelines, memory structure etc.
No signs indicate it could be possible even in 5-10 yeeas.

 

[bkat]

now the best flow of SYSTEM C is SYSTEM C -- verilog RTL -- GDS II

Good Luck

 

[bigyellow]

I think SystemC is hardly accepted by industry recently. especially in RTL and lower level. It is far from the vhdl and verilog. I think systemverilog and VHDL 200X may be better.

 

[omara007]

so why SystemC people keep saying that you can use SystemC in system level modeling and when it comes to RTL you can use the same code with override/overload/re-implement things ?? .. is this a fake ?

In other words, what's the benfit of SystemC for system level over the ordinary matlab flow as long as i'm not gonna get reuse the same SystemC code in RTL with modification !!! ..

and Why is there some books like SystemC Primer for J. Bhaskar ? .. this book targets SystemC RTL !!! .. why should we write RTL if we are not going to synthesize it !

Added after 2 hours 16 minutes:

AlexWan ..
Will the Magma VLSI Compiler tool take SystemC at the front-end and synthesize it maturely ? .. I guess if this is the case, then the problem is solved .. because it's all about synthesizing SystemC maturely!

ha ?

 

[AlexWan]

Hi, omara007

I am sorry, the answer is "No". VLSI Compiler only support RTL as input source.

I think the SystemC is suitable for model language. We can't control precise the circuit with high level tools and language. So todays, Verilog is good language for producting the GDSII.

Good Lcuk

 

[bigyellow]

Well. I think SystemC will have good future in academic. But hardly accepted by industry.

 

[omara007]

AlexWan

What do you exactly mean by RTL ? .. only VHDL and Verilog ? .. Actually SystemC supports writing RTL code .. and this is what SystemC Primer for Bhaskar was for ..

folks..
What about those Sysnthesis Tools for SystemC ? .. what about Xilinx support for SystemC ? .. what about Synopsis ? .. doesn't Synopsis build a synthesis tool for it ? .. how efficient is it ! ..

The 1 million dollar question is : Why people keep using 2 different languages for system-level modeling and for RTL !! .. why do they keep threwing away system code and start from the very begining for RTL ??

 

[manaman]

At first place i am wondering why are you people so obsessed with writing RTL code in SystemC ,We have observed that the effort to write RTL with SystemC is much higher than Verilog/VHDL , also the simulations will not be run faser
SystemC is best for TLM , the effrot invloved is less , you can get anyway higher than 100x simulation speed , also you can have the freedom of devloping the drivers at an early stage of design , of course it is the best tool for architectural simulation
Fit the best tools into the suitable parts of your flow , use Verilog/VHDL for RTL use SystemC at TLM abstraction

 

[omara007]

Good manaman ..
but we will still be putting the system-level code in the trash can after done with verification! .. in other words, the code won't propagate from System Level to RTL if we are going to use SystemC for system-level and Verilog for RTL .. which means we will still be wasting the code ..
in verilog RTL we start from the beginging again .. but if we managed to write SystemC RTL with good synthesis .. then the won't need to start from the beginging again .. no need to re-invent the wheel ..

 

[mint]

Hi omara007,

I agree with you. It is total waste of effort. Remember that each rewrite require verification and validation again.

The problem is the lack or non-existent of logic synthesis tool for RTL SystemC ( yes guys, SystemC do support RTL coding not only system level ). The Synopsys's SystemC synthesis tool has been discontinued. So there is no tool for ASIC.

Like what you said Xilinx currently include SystemC synthesis but I don't know how good it is. Current best bet can be this

System Level SystemC -> RTL SystemC -> translate to Verilog/VHDL -> synthesis

There are several tools in the market that can translate RTL SystemC to Verilog so you don't need to do that manually.

Another option could be using graphical design tool like Summit and then translate it to whichever RTL language you like. But that can be another topic for debate ;-) [/list]

 

[bigyellow]

I think SystemC is hard to be accepted by industry, especially in ASIC design. There are a lot of risks and cost.

For example, convert system level SystemC codes to synthesisable SystemC code aslo need some work. Company aslo need defined new coding rules for synthesisable SystemC code, systemC is not mature. There are too few experienced expert with SystemC, it is hard to control in a project.

Verilolg and VHDL will continue dominate the market, especially in ASIC. There are a lot of reused codes in verilog and VHDL, and lots of experienced designer which can be easily and safely used in their project.

As you said there is no reason to use 2 different languages in system level and RTL level. So I think Systemverilog and VHDL 200X which can cover both levels will be the future in industry.

 

[manaman]

Good manaman ..
but we will still be putting the system-level code in the trash can after done with verification! .. in other words, the code won't propagate from System Level to RTL if we are going to use SystemC for system-level and Verilog for RTL .. which means we will still be wasting the code ..
in verilog RTL we start from the beginging again .. but if we managed to write SystemC RTL with good synthesis .. then the won't need to start from the beginging again .. no need to re-invent the wheel ..

Hi
What I want to say is that the propagation from a TLM SystemC model to RTL Systemc model is more painful than writing RTL Verilog , Another point I want to add is we are not throwing away the TLM nodels they will remain in the enviorment right from architecture simulation to say accleration /emulation .Only the DUT abstration levels will be changed during the design life cycle , If you are Interating an Soc the said TLM views of IP s are avilable of the shelf ,

Regards

 

[omara007]

hi mint ..
is it mature to convert SystemC RTL presentation to Verilog or VHDL automatically thru a tool ? .. I mean this definetly won't be accurate, but to what extent is this translation can be accepted in industry ..?

 

[AlexWan]

Hi, omara007,

Only Verilog or VHDL.

No few synthesis tools support the SystemC RTL. I check the book of Bhaskar, but I can't find the clear tools for synthesis the RTL of SystemC.

Good Luck

 

[mint]

Hi Omara007,

One tool, Forte Cynthesizer, got good reviews from companies in Japan. You can read it all on deepchip. But Forte Cynthesizer is mostly for datapath and it is more of a behavioural synthesis tool. Prosilog also has a SystemC to VHDL tool. In terms of maturity, Forte is the one.

 

[Arnold]

Coding in SystemC is difficult as C is a procedure programming language instead of functional language. You had to take care of memory allocation, etc. It's too difficult for hardware designer