vGoodtimes
I have another question about this sentece that you mentioned earlier.
"RTL developers prefer to have modules with registered outputs and inputs when possible."
So you mean that I have to store Utemp (which is a serial input) in A FF first?
and then just use the FF instead?
it is like causing a delay (for one clock pulse)
is that what mean?
vGoodtimes
I have another question about this sentece that you mentioned earlier.
"RTL developers prefer to have modules with registered outputs and inputs when possible."
So you mean that I have to store Utemp (which is a serial input) in A FF first?
and then just use the FF instead?
it is like causing a delay (for one clock pulse)
is that what mean?
vGoodtimes
I have another question about this sentece that you mentioned earlier.
"RTL developers prefer to have modules with registered outputs and inputs when possible."
So you mean that I have to store Utemp (which is a serial input) in A FF first?
and then just use the FF instead?
it is like causing a delay (for one clock pulse)
is that what mean?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity OEncoder_3 is Generic (K : integer range 0 to 10 :=4;-- K bits for Message N : integer range 0 to 20 :=7);-- N bits for Codeword Port ( Data_in : in STD_LOGIC; Data_out : out STD_LOGIC; Clk : in STD_LOGIC; Reset : in STD_LOGIC; Valid_in : in STD_LOGIC; Valid_out : out STD_LOGIC); end OEncoder_3; architecture Behavioral of OEncoder_3 is --Constant Declaration Constant GP : STD_LOGIC_VECTOR ((N-K) downto 0) :="1011"; -- Generator Polynomial of (N-K) Degree --Signal Declaration Signal D,Q : STD_LOGIC_VECTOR ((N-K-1) downto 0) :=(Others => '0'); -- Flip flop's Inputs Signal ClockCounter : integer range 0 to N; Signal GTemp,UQX : STD_LOGIC; Signal Input_Buffer : STD_LOGIC; Type Switch is ( Parity , message ); Signal Switch2 : Switch := Message; begin --Combinatorial Part --1)- taking care of FF's Input and XORs --***CHECKED*** Gen1:for i in 1 to N-K-1 generate D(i) <= (Gtemp xor Q(i-1)) when GP(i)='1' else Q(i-1); end generate; D(0) <= Gtemp; ------------------------------------------------------------------------------------------- --2) taking care of FF's Outputs --***CHECKED*** UQX <= (Input_Buffer xor Q(N-K-1)) When (Input_Buffer = '0' or Input_Buffer='1') else '0'; -------------------------------------------------------------------------------------------- --3) taking care of GATE --***CHECKED*** Gtemp <= UQX when Switch2 = Message else '0'; -- Gtemp <= UQX and Switch2 -------------------------------------------------------------------------------------------- -- taking care of Switch 2 --4)***CHECKED*** Data_out <= Input_Buffer When Switch2 = Message else Q(N-K-1); -------------------------------------------------------------------------------------------- -- Sequential part Process(Clk,Reset) begin if( Reset = '0') then Q <= (Others => '0'); ClockCounter <= 0; Switch2 <= Message; Input_Buffer <= '0'; elsif (rising_edge(Clk) and Valid_in ='1' )then Input_Buffer <= Data_in; Valid_out <= '1'; Q <= D; if (Input_Buffer = '0' or Input_Buffer = '1') then if (ClockCounter < N - 1) then ClockCounter <= ClockCounter + 1; elsif (ClockCounter = N - 1) then Valid_out <= '0'; end if; end if; if (ClockCounter = K - 1) then Switch2 <= Parity; end if; end if; end process; end Behavioral;
-- This process will either drive "Data_out" or "Data_buf" where "Data_out <= Data_buf;" is outside this process.
-- Data_buf is used when bits of Data_out are used within this entity. VHDL doesn't allow outputs to be used within the same architecture.
Process(Clk,Reset)
-- any variables for purely combinatorial logic here.
begin
if( Reset = '0') then
-- all signals assigned in this process given constant default values here.
elsif (rising_edge(Clk)) then
-- if you had any variables declared, use them here. Ensure they do no generate registers -- never use a variable before it is assigned.
-- default assignments here
Valid_out <='0'; -- default to '0'.
-- The core logic
if (Valid_in = '1') then
-- logic for the "input is valid case here"
elsif (Switch2 = Parity) then
-- logic for the parity case here
end if;
end if;
end process;
process(clk, reset)
begin
if rising_edge(clk) then
--synchronous code here
end if;
if reset = '1' then
--reset only things you really want to reset here
end if;
end process;
4. There is also the issue that you have signals assigned in the clocked part of the process and not in the reset. This will mean that the async reset will be used as part of the clock enable on that signal, so when reset = '1' it will not set that register. This is possibly bad because the reset could be asserted at any point, and violate a setup time. There are two ways to fix this:
a) Assign all signals in the process in the reset.
b) use the "post clock reset" template for your code:
Code:process(clk, reset) begin if rising_edge(clk) then --synchronous code here end if; if reset = '1' then --reset only things you really want to reset here end if; end process;
This means you can mix up signals with and without async reset in the same process, without generating extra clock enables. Again, you'll probably get resistance from many engineers because it doesnt conform to the "correct" template - but it works perfectly fine in all synthesisors.
process(clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- Synchronous reset
-- This style is only good if all signals are resetted here
else
-- Synchronous code here
end if;
end if;
end process;
process(clk, reset)
begin
if rising_edge(clk) then
-- Synchronous code here
if reset = '1' then
-- Synchronous reset
-- Skip signals that don't need to be resetted
end if;
end if;
end process;
4. There is also the issue that you have signals assigned in the clocked part of the process and not in the reset. This will mean that the async reset will be used as part of the clock enable on that signal, so when reset = '1' it will not set that register. This is possibly bad because the reset could be asserted at any point, and violate a setup time.
I don't realize at first sight which problem you are referring to. Where do you see an unintended clock enable?
Possible violation of setup times by an asynchronous reset is a general problem which can be only avoided by synchronizing the reset. Without an explicit reset, the problem is shifted to possible POR to clock setup violations.
I don't realize at first sight which problem you are referring to. Where do you see an unintended clock enable?
process(clk, reset)
begin
if reset = '1' then
-- Asynchronous reset
-- This style is only good if all signals are resetted here
elsif rising_edge(clk) then
-- Synchronous code here
end if;
end if;
end process;
process(clk, reset)
begin
if rising_edge(clk) then
--synchronous code here
end if;
if reset = '1' then
--reset only things you really want to reset here
end if;
end process;
Code:
process(clk, reset)
begin
if rising_edge(clk) then
--synchronous code here
end if;
if reset = '1' then
--reset only things you really want to reset here
end if;
end process;
Normally, the release should be synchronous. There are cases where it doesn't matter, but the analysis will probably cost more than going safe with synchronous release (which will only cost 2 registers).Just one question. Does the signal reset need to be released synchronously (managed in another process)?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 entity OEncoder_3v2 is Generic (K : integer range 0 to 10 :=4;-- K bits for Message N : integer range 0 to 20 :=7);-- N bits for Codeword Port ( Data_in : in STD_LOGIC; Data_out : out STD_LOGIC; Clk : in STD_LOGIC; Reset : in STD_LOGIC; Valid_in : in STD_LOGIC; Valid_out : out STD_LOGIC); end OEncoder_3v2; architecture Behavioral of OEncoder_3v2 is --Constant Declaration Constant GP : STD_LOGIC_VECTOR ((N-K) downto 0) :="1011"; -- Generator Polynomial of (N-K) Degree --Signal Declaration Signal D,Q : STD_LOGIC_VECTOR ((N-K-1) downto 0) :=(Others => '0'); -- Flip flop's Inputs Signal ClockCounter : integer range 0 to N; Signal GTemp,UQX : STD_LOGIC; Signal Input_Buffer,Vin_Buffer,Vout_Buffer : STD_LOGIC; Type Switch is ( Parity , message ); Signal Switch2 : Switch := Message; begin --Combinatorial Part --1)- taking care of FF's Input and XORs --***CHECKED*** Gen1:for i in 1 to N-K-1 generate D(i) <= (Gtemp xor Q(i-1)) when GP(i)='1' else Q(i-1); end generate; D(0) <= Gtemp; ------------------------------------------------------------------------------------------- --2) taking care of FF's Outputs --***CHECKED*** UQX <= (Input_Buffer xor Q(N-K-1)) When (Vin_Buffer = '1') else '0'; -------------------------------------------------------------------------------------------- --3) taking care of GATE --***CHECKED*** Gtemp <= UQX when Switch2 = Message else '0'; -- Gtemp <= UQX and Switch2 -------------------------------------------------------------------------------------------- -- taking care of Switch 2 --4)***CHECKED*** Data_out <= Input_Buffer When Switch2 = Message else Q(N-K-1); -------------------------------------------------------------------------------------------- -- taking care of Valid Out --5)***CHECKED*** Valid_out <= Vout_Buffer; -- Sequential part Va Process(Clk,Reset) begin if rising_edge(clk) then if reset='1' then -- reset all assigned signals here Q <= (Others => '0'); ClockCounter <= 0; Input_Buffer <= '0'; Vout_Buffer <= '0'; Vin_Buffer <= '0'; Switch2 <= Message; else -- Default assignments first Q <= D; Input_buffer <= Data_in; Vin_Buffer <= Valid_in; if (Vin_Buffer = '1') then if (ClockCounter < N - 1) then ClockCounter <= ClockCounter + 1; Vout_Buffer <= '1'; elsif (ClockCounter = N - 1) then Vout_Buffer <= '0'; end if; end if; if (ClockCounter = K-1) then Switch2 <= Parity; end if; end if;--Reset end if;--Clock end Process; end Behavioral;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Process(Clk,Reset) begin if rising_edge(clk) then -- data WHY would you reset the data!? -- You have a valid it doesn't need a reset. if reset = '1' then Q <= (others => '0'); Input_Buffer <= '0'; Vin_Buffer <= '0'; else Q <= D; Input_buffer <= Data_in; Vin_Buffer <= Valid_in; end if; -- your counter doesn't count after it reaches N-1 -- it saturates at N-1 and stays there forever. if reset = '1' then ClockCounter <= 0; elsif (Vin_Buffer = '1') then if (ClockCounter < N - 1) then ClockCounter <= ClockCounter + 1; end if; end if; -- Generate an output valid signal for next stage if reset = '1' then Vout_Buffer <= '0'; elsif (Vin_Buffer = '1') then if (ClockCounter < N - 1) then Vout_Buffer <= '1'; else Vout_Buffer <= '0'; end if; end if; -- So you hammer on the reset for everything to load a message? -- you shouldn't call this a reset it's really a load_msg signal -- you also need to learn how to name things that make sense to -- someone else that will have to read the code in the future. -- like Vout_Buffer implies to me it's a buffered Vout not a registered -- Valid output...Valid_reg makes more sense to me if I was glancing -- at the code. if reset = '1' then Switch2 <= Message; elsif (ClockCounter = K-1) then Switch2 <= Parity; end if; end if;--Clock end Process;
Hi,
thanks alot ads_ee, for your tips and advices
I will try to do this coding thing your way, but right now
all I care is to get some answers.
Because it's my final project and my Professor doesn't read the code,
he just checks the inputs and outputs.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 entity OEncoder_3v2 is Generic (K : integer range 0 to 10 :=4;-- K bits for Message N : integer range 0 to 20 :=7);-- N bits for Codeword Port ( Data_in : in STD_LOGIC; Data_out : out STD_LOGIC; Clk : in STD_LOGIC; Reset : in STD_LOGIC; Valid_in : in STD_LOGIC; Valid_out : out STD_LOGIC); end OEncoder_3v2; architecture Behavioral of OEncoder_3v2 is --Constant Declaration Constant GP : STD_LOGIC_VECTOR ((N-K) downto 0) :="1011"; -- Generator Polynomial of (N-K) Degree --Signal Declaration Signal D,Q : STD_LOGIC_VECTOR ((N-K-1) downto 0) :=(Others => '0'); -- Flip flop's Inputs Signal ClockCounter : integer range 0 to N; Signal GTemp,UQX : STD_LOGIC; Signal Input_Buffer,Vin_Buffer : STD_LOGIC; Type Switch is ( Parity , message ); Signal Switch2 : Switch := Message; begin --Combinatorial Part --1)- taking care of FF's Input and XORs --***CHECKED*** Gen1:for i in 1 to N-K-1 generate D(i) <= (Gtemp xor Q(i-1)) when GP(i)='1' else Q(i-1); end generate; D(0) <= Gtemp; ------------------------------------------------------------------------------------------- --2) taking care of FF's Outputs --***CHECKED*** UQX <= (Input_Buffer xor Q(N-K-1)) When (Vin_Buffer = '1') else '0'; -------------------------------------------------------------------------------------------- --3) taking care of GATE --***CHECKED*** Gtemp <= UQX when Switch2 = Message else '0'; -- Gtemp <= UQX and Switch2 -------------------------------------------------------------------------------------------- -- taking care of Switch 2 --4)***CHECKED*** Data_out <= Input_Buffer When Switch2 = Message else Q(N-K-1); -------------------------------------------------------------------------------------------- Valid_out <= '0' When ClockCounter = N else Vin_Buffer; -- Sequential part Va Process(Clk) begin if rising_edge(clk) then if reset='1' then -- reset all assigned signals here Q <= (Others => '0'); ClockCounter <= 0; Input_Buffer <= '0'; --Output_Buffer <= '0'; --Vout_Buffer <= '0'; Vin_Buffer <= '0'; Switch2 <= Message; else -- Default assignments first Q <= D; Vin_Buffer <= Valid_in; Input_Buffer <= Data_in; if Vin_Buffer ='1' then if ClockCounter < N then ClockCounter <= ClockCounter + 1; end if; end if; if ClockCounter = K-1 then Switch2 <= Parity; end if; end if;--Reset end if;--Clock end Process; end Behavioral;
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?