mohamed mahmoud
Junior Member level 1
i,am very new to "SystemVerilog for Verification"
question :
i have written code with vhdl , is it possible to write testbenchs with system verilog to verify my ''vhdl'' code ??
if it yes : hopefully anyone to provide tutorials about system verilog (i don,t need slides that has small information and also don,t need big reference)
question :
i have written code with vhdl , is it possible to write testbenchs with system verilog to verify my ''vhdl'' code ??
if it yes : hopefully anyone to provide tutorials about system verilog (i don,t need slides that has small information and also don,t need big reference)