System verilog Integer and logic literals

[yourcheers]

Form system verilog LRM 3.1a,
SystemVerilog adds the ability to specify unsized literal single bit values with a preceding apostrophe ( ’ ), but
without the base specifier. All bits of the unsized value are set to the value of the specified bit. In a self-determined
context these literals have a width of 1 bit, and the value is treated as unsigned.
’0, ’1, ’X, ’x, ’Z, ’z // sets all bits to this value


I am having doubt regarding "In a self-determined context these literals have a width of 1 bit, and the value is treated as unsigned."
It is specified that variable is treated as unsigned, if that is the case "integer a = `1;" is saved with 32'hFFFFFFFF or 32'h7FFFFFF ??

 

[dave_59]

First, please get a free copy of the latest SystemVerilog LRM.

Your example is not a self-determined context. All of the bits of a will be set to 1. So the result is -1.