system verilog event issue

deepa122 · May 11, 2011

I have a event emitted from a design file deep down in the DUT heirarchy, I want to capture this event in my testbench(TB). Is this possible in system verilog. If yes, then how ??

ljxpjpjljx · May 12, 2011

you can use hierachical refer for this signal in system verilog testbench

deepa122 · May 12, 2011

If its a signal, hierarchical referencing helps, but for event it doesn't help... Or i dont know if there is a different way to refer to a event in the hierarchy..!!

system verilog event issue

deepa122

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ljxpjpjljx

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deepa122

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system verilog event issue

deepa122

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deepa122

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