system verilog event issue

[deepa122]

I have a event emitted from a design file deep down in the DUT heirarchy, I want to capture this event in my testbench(TB). Is this possible in system verilog. If yes, then how ??

 

[ljxpjpjljx]

you can use hierachical refer for this signal in system verilog testbench

 

[deepa122]

If its a signal, hierarchical referencing helps, but for event it doesn't help... Or i dont know if there is a different way to refer to a event in the hierarchy..!!