System Verilog Design a signal flag.

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quocviet19501

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Hi all, in my system verilog project. I am stuck because of a signal below
In this design, done_en is a flag that keeps tract of the generation of 2 bit data_fail. When the generation complete, the done signal asserts for 1 clk cycle to indicate data generation is finished. But I cannot find any way to control this signal like the above diagram.
Please if anyone provide any hint, I would really appreciate it.

 

Solution
Code: 
if rising edge (clk) then
   done_en <= not empty;
   done <= done_en and empty;
end if;
respectively
Code: 
always_ff@(posedge clk)
begin
   done_en <= !empty;
   done <= done_en & empty;
end
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Hi,

as the picture shows:
doen_en is generated from empty
done_en is clocked by the rising edge of clk.

So my approah would be:
a simple DFF:
* CLK --> DFF_CLK
* empty --> inverted --> DFF_D
* DFF_Q --> done_en

Klaus
 

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KlausST said:
Hi,

as the picture shows:
doen_en is generated from empty
done_en is clocked by the rising edge of clk.

So my approah would be:
a simple DFF:
* CLK --> DFF_CLK
* empty --> inverted --> DFF_D
* DFF_Q --> done_en

Klaus
Click to expand...
My question is how to design the signal "done" that asserts 1 clk cycle like the above picture. This is where I am stuck. But thank you very much for your reply.
 

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in a clocked process:
done_en_d <= done_en;

combinatorial:
done <= done_en_d and not done_en;
 

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Code: 
if rising edge (clk) then
   done_en <= not empty;
   done <= done_en and empty;
end if;
respectively
Code: 
always_ff@(posedge clk)
begin
   done_en <= !empty;
   done <= done_en & empty;
end
 

Upvote 0 Downvote
Solution
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